• Title/Summary/Keyword: 전류 신호

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High Noise Margin LVDS I/O Circuits for Highly Parallel I/O Environments (다수의 병렬 입.출력 환경을 위한 높은 노이즈 마진을 갖는 LVDS I/O 회로)

  • Kim, Dong-Gu;Kim, Sam-Dong;Hwang, In-Seok
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.44 no.1
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    • pp.85-93
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    • 2007
  • This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

Design of 3-bit Arbitrary Logic Circuit based on Single Layer Magnetic-Tunnel-Junction Elements (단층 입력 구조의 Magnetic-Tunnel-Junction 소자를 이용한 임의의 3비트 논리회로 구현을 위한 자기논리 회로 설계)

  • Lee, Hyun-Joo;Kim, So-Jeong;Lee, Seung-Yeon;Lee, Seung-Jun;Shin, Hyung-Soon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.12
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    • pp.1-7
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    • 2008
  • Magnetic Tunneling Junction (MTJ) has been used as a nonvolatile universal storage element mainly in memory technology. However, according to several recent studies, magneto-logic using MTJ elements show much potential in substitution for the transistor-based logic device. Magneto-logic based on MTJ can maintain the data during the power-off mode, since an MTJ element can store the result data in itself. Moreover, just by changing input signals, the full logic functions can be realized. Because of its programmability, it can embody the reconfigurable magneto-logic circuit in the rigid physical architecture. In this paper, we propose a novel 3-bit arbitrary magneto-logic circuit beyond the simple combinational logic or the short sequential one. We design the 3-bit magneto-logic which has the most complexity using MTJ elements and verify its functionality. The simulation results are presented with the HSPICE macro-model of MTJ that we have developed in our previous work. This novel magneto-logic based on MTJ can realize the most complex logic function. What is more, 3-bit arbitrary logic operations can be implemented by changing gate signals of the current drivel circuit.

A New Variable Degeneration Resistor for Digitally Programmable CMOS VGA (디지털 방식의 이득조절 기능을 갖는 CMOS VGA를 위한 새로운 가변 축퇴 저항)

  • Kwon, Duck-Ki;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of IKEEE
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    • v.7 no.1 s.12
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    • pp.43-55
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    • 2003
  • A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome the problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. The proposed gain control scheme makes it easy to implement a low-voltage and high-speed VGA. This paper describes the problems existed in conventional methods, the principle and advantages of the proposed scheme, and their performance comparison in detail. A CMOS VGA cell is designed using the proposed degeneration resistor. The 3dB bandwidths are greater than 650㎒ and the gain errors are less than 0.3dB in a gain control range from -12dB to +12dB in 6dB steps. It consumes 3.1㎃ from a 2.5V supply voltage.

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Au-Sn합금 도금층의 접촉저항 및 솔더퍼짐성에 미치는 Sn함량의 영향

  • Park, Jae-Wang;Son, In-Jun
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2017.05a
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    • pp.130-130
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    • 2017
  • Au 합금 도금층은 내마모성 및 내식성이 우수하고 접촉저항이 낮기 때문에, 커넥터, 인쇄회로기판 등과 같은 전자부품의 접속단자부에 널리 적용되고 있다. 각 부품들을 효과적으로 전기적 신호를 통해 연결하기 위해서는 낮은 접촉저항이 요구되며, 이러한 Au 합금 도금층의 접촉저항은 합금 원소의 종류 및 함량, 용융 솔더와 전자부품을 고정시키는 표면실장공정에서 받는 theremal aging의 온도와 시간에 따라 변화된다. 현재 전자부품용 커넥터에 실시되고 있는 금 합금도금은 Au-0.3wt%Co합금, Au-0.2wt%Ni합금도금이 대부분 적용되고 있으며, 높은 순도(금 함유량 99.7wt%이상)로 인하여 금 사용량을 절감하기 어려운 실정이다. Sn은 Au와 높은 고용률을 갖는 합금을 형성하는 장점을 갖고 있기에 금 사용량 절감에 큰 기여를 할 수 있을 것으로 예상된다. 따라서 본 연구에서는 Sn을 합금 원소로 사용하여 높은 Sn함량을 갖는 Au 합금 도금층을 제작하고, 무연솔더의 융점보다 더 높은 온도인 533K에서 thermal aging을 실시하여, Sn함량별로 thermal aging에 따른 접촉저항과 솔더퍼짐성의 변화를 기존의 Co, Ni합금과 비교 조사하였다. 또한, 표면분석을 통하여 Au-Sn합금 도금층의 접촉저항이 변화하는 요인에 대해서도 고찰하였다. 표면적 $0.2dm^2$의 순수 동 시편 위에 약 $2{\mu}m$두께의 Ni도금을 실시한 후 Sn 함량을 다르게 준비한 도금 용액(Au 6g/L, Sn 1~8g/L)을 사용하여 Au-Sn합금 도금을 실시하였다. Au-Sn합금 도금층은 전류밀도 0.5ASD, 온도 $40^{\circ}C$에서 약 $0.1{\mu}m$두께가 되도록 도금하였으며, 두께는 형광X선 도금두께측정기로 측정하였다. 금 합금 도금층 내의 Sn함량은 Ti시편 위에 도금한 Au-Sn합금층을 왕수에 용해시킨 다음, ICP를 사용하여 분석하였다. Au-Sn합금 도금층의 접촉저항은 준비된 시편을 533K에서 1분 30초, 3분, 6분 간 열처리한 후, 5회 접촉저항을 측정하여 그 평균값으로 하중에 따른 금 합금 도금층의 접촉저항을 비교하였다. 솔더링성은 솔더볼을 합금 표면에 솔더페이스트를 이용하여 붙인 뒤 533K에서 30초간 열처리하고, 열처리 후 솔더볼의 높이 변화를 측정해 열처리 전 솔더볼의 높이에 비해 퍼진정도를 측정하였다. 또한, 도금층 내의 Sn함량에 따라서 접촉저항이 변화하는 요인을 분석하기 위해서 X선 광전자 분광기를 이용하여 도금층 표면의 정량 분석 및 화학적 결합상태를 분석하였다. ICP분석결과 Au-Sn합금층 내의 Sn함량은 도금용액의 조성별로 9~12wt% Sn 합금층이 형성된 것을 알 수 있었고 기존의 Au-Ni, Au-Co 합금층과 비교해 합금함량이 크게 증가된 것을 알 수 있었다. 또한 접촉저항 측정 결과, 기존의 Au-Ni, Au-Co합금층의 접촉저항과 비교했을 때 Au-Sn합금층의 접촉저항이 더 낮은 것을 알 수 있었다. 또한, 솔더퍼짐성 측정 결과 기존의 Au-Ni, Au-Co합금층과 비교해 솔더퍼짐성이 우수한 것을 확인할 수 있었다. 따라서 전자부품용 접점재료에 합금함량이 높은 Au-Sn합금층을 적용시키면 더 우수한 커넥터의 성능을 얻을 수 있을 뿐 아니라 경제적으로 큰 절약 효과를 기대할 수 있을 것으로 판단된다.

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A VHF/UHF-Band Variable Gain Low Noise Amplifier for Mobile TV Tuners (모바일 TV 튜너용 VHF대역 및 UHF 대역 가변 이득 저잡음 증폭기)

  • Nam, Ilku;Lee, Ockgoo;Kwon, Kuduck
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.12
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    • pp.90-95
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    • 2014
  • This paper presents a VHF/UHF-band variable gain low noise amplifier for multi-standard mobile TV tuners. A proposed VHF-band variable gain amplifier is composed of a resistive shunt-feedback low noise amplifier to remove external matching components, a single-to-differential amplifier with input PMOS transcoductors to improve low frequency noise performance, a variable shunt-feedback resistor and an attenuator to control variable gain range. A proposed UHF-band variable gain amplifier consists of a narrowband low noise amplifier with capacitive tuning to improve noise performance and interference rejection performance, a single-to-differential with gm gain control and an attenuator to adjust gain control range. The proposed VHF-band and UHF-band variable gain amplifier were designed in a $0.18{\mu}m$ RF CMOS technology and draws 22 mA and 17 mA from a 1.8 V supply voltage, respectively. The designed VHF-band and UHF-band variable gain amplifier show a voltage gain of 27 dB and 27 dB, a noise figure of 1.6-1.7 dB and 1.3-1.7 dB, OIP3 of 13.5 dBm and 16 dBm, respectively.

Analysis of Electrical and Optical Characteristics of Silicon Based High Sensitivity PIN Photodiode (Silicon기반 고감도 PIN Photodiode의 전기적 및 광학적 특성 분석)

  • Lee, Jun-Myung;Kang, Eun-Young;Park, Keon-Jun;Kim, Yong-Kab;Hoang, Geun-Chang
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.6
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    • pp.1407-1412
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    • 2014
  • In order to improve spectrum sensitivity of photodiode for detection of the laser at 850 nm ~ 1000 nm of near-infrared wavelength band, this study has produced silicon-based fast film PIN photodiode and analyzed electrical and optical properties. The manufactured device is packaged in TO-18 type. The electrical properties of the dark currents both Anode 1 and Anode 2 have valued of approximately 0.055 nA for 5 V reverse bias, while the capacitance showed 19.5 pF at frequency range of 1 kHz and about 19.8 pF at the range of 200 kHz for 0 V. In addition, the rising time of output signal was verified to have fast response time of about 30 ns for 10 V. For the optical properties, the best spectrum sensitivity was 0.66 A/W for 880 nm, while it was relatively excellent value of 0.45 A/W for 1,000 nm.

Study on the method of safety diagnosis of electrical equipments using fuzzy algorithm (퍼지알고리즘을 이용한 전기전자기기의 안전진단방법에 대한 연구)

  • Lee, Jae-Cheol
    • Journal of Digital Convergence
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    • v.16 no.7
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    • pp.223-229
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    • 2018
  • Recently, the necessity of safety diagnosis of electrical devices has been increasing as the fire caused by electric devices has increased rapidly. This study is concerned with the safety diagnosis of electric equipment using intelligent Fuzzy technology. It is used as a diagnostic input for the multiple electrical safety factors such as the use current, cumulative use time, deterioration and arc characteristics inherent to the equipment. In order to extract these information in real time, a device composed of various sensor circuits, DSP signal processing, and communication circuit is implemented. The fuzzy logic algorithm using the Gaussian function for each information is designed and compiled to be implemented on a small DSP board. The fuzzy logic receives the four diagnostic information, deduces it by the fuzzy engine, and outputs the overall safety status of the device as a 100-step analog fuzzy value familiar to human sensibility. By experiments of a device that combines hardware and fuzzy algorithm implemented in this study, it is verified that it can be implemented in a small DSP board with human-friendly fuzzy value, diagnosing real-time safety conditions during operation of electric equipment. In the future, we expect to be able to study more intelligent diagnostic systems based on artificial intelligent with AI dedicated Micom.

Design and Implementation of the Mutually Coupled Structure Oscillators for Improved Phase-Noise Characteristics (위상 잡음 특성 개선을 위한 상호 결합 구조의 발진기 설계 및 제작)

  • Choi, Jeong-Wan;Do, Ji-Hoon;Lee, Hyung-Kyu;Kang, Dong-Jin;Yoon, Ho-Seok;Lee, Kyung-Hak;Hong, Ui-Seok
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.11 s.114
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    • pp.1112-1119
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    • 2006
  • In this paper, mutually coupled oscillator is employed to improve phase noise. Mutually coupled structure oscillator couples two oscillator's phase shifted output signals, that is fabricated using teflon board which has dielectric constant of 2.5 and Surface Mount Gallium Arsenide FET devices. And this paper proposed the structure to bias adjustment for the phase condition of mutually couples. When one oscillator has bias point of 4.4 V and 37 mA, it's output signal has phase noise characteristic of -96.37 dBc(@9305 MHz, offset frequency 100 KHz), -73.46 dBc(10 kHz). and After it's output signal mutually coupled the other's output signal that has bias point of 8.1 V and 69 mA, it has superior phase noise characteristic of -106.7 dBc(@9305 MHz, offset frequency 100 kHz), -81 dBc(10 kHz).

A study on digital locking device design using detection distance 13.4mm of human body sensing type magnetic field coil (인체 감지형 자기장 코일의 감지거리 13.4mm를 이용한 디지털 잠금장치 설계에 관한 연구)

  • Lee, In-Sang;Song, Je-Ho;Bang, Jun-Ho;Lee, You-Yub
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.1
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    • pp.9-14
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    • 2016
  • This study evaluated a digital locking device design using detection distance of 13.4mm of a human body sensing type magnetic field coil. In contrast to digital locking devices that are used nowadays, the existing serial number entering buttons, lighting, number cover, corresponding pcb, exterior case, and data delivery cables have been deleted and are only composed of control ON/OFF power switches and emergency terminals. When the magnetic field coil substrates installed inside the inner case detects the electric resistance delivered from the opposite side of the 12mm interval exterior contacting the glass body part, the corresponding induced current flows. At this time, the magnetic field coil takes the role as a sensor when coil frequency of the circular coil is transformed. The magnetic coil as a sensor detects a change in the oscillation frequency output before and after the body is detected. This is then amplified to larger than 2,000%, transformed into digital signals, and delivered to exclusive software to compare and search for embedded data. The detection time followed by the touch area of the body standard to a $12.8{\emptyset}$ magnetic field coil was 30% contrast at 0.08sec and 80% contrast at 0.03sec, in which the detection distance was 13.4mm, showing the best level.

Loss Properties of Nano-crystalline Alloy coated as a Resistive Layer (표면 저항층 형성에 의한 나노결정 합금재료의 손실 특성)

  • Kim, Hyun-Sik;Kim, Jong-Ryung;Lee, Geene;Lee, Hae-Yeon;Huh, Jung-Sub;Oh, Young-Woo;Byun, Woo-Bong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.11a
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    • pp.229-229
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    • 2007
  • 나노결정 합금재료를 전력선 통신 커플러용 자심재료로 응용하기 위해서는 고주파 대역에서의 손실 특성이 제어되어야 한다. 즉 고속 전력선 통신을 위한 자심재료의 투자율 및 완화 주파수 등의 전자기적 특성은 30MHz까지 우수하고 안정적으로 유지되어야 하며, 높은 투자율 및 자속밀도, 공진주파수뿐만 아니라 낮은 전력손실 값을 가져야 한다. 따라서 본 연구에서는 나노결점 합금 리본 표면에 딥 코팅, 졸-겔법, 진공함침 등의 방법을 이용하여 PZT, $TiO_2$$SiO_2$ 등의 산화물 고저항층을 형성시켜 자기적 성질을 유지하면서 고주파 대역의 와전류 손실을 감소시켜 통신용 자심재료로의 응용성을 향상시키고자 하였다. PZT 슬러리의 제타전위 조절을 통해 최적의 분산조건을 얻을 수 있었고, 평균 150nm인 PZT 입자의 초미립자와 가소제, 분산제, 결합제의 첨가조건을 확립할 수 있었다. 딥-코팅은 슬러리 내 유지시간 10초, 인상속도 5mm/min로 30회 반복되었을 때 가정 우수한 특성을 나타내었으며, 고주파 대역에서의 손실 감소효과를 나타내었다. 그리고 졸-겔법에 의해 제조된 슬러리를 이용한 $TiO_2$$SiO_2$ 산화물 저항층 코팅을 통해 금속 알콕사이드의 혼합조건 및 저항층 형성용 슬러리의 제조조건을 확립하였고, 합금 리본표면에 균일하고 우수한 점착력을 가지는 저항층을 형성시킬 수 있었으며, 이에 따른 코어손실의 감소효과를 나타낼 수 있었다. 또한 진공 함침법을 통한 저항층 형성에서, $TiO_2$ 나노분말을 표면 저항층으로 코팅했을 때, 가장 높은 코어손실 감소효과를 나타내었다. 한편, 표면 저항층이 형성된 나노결정 합금으로 제조한 자심재료를 이용하여 전력선 통신용 비접촉식 커플러에의 적용과 시험을 통해 고주파 손실 감소효과에 의한 신호전송 특성과 전류특성을 향상시킬 수 있었다.

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