• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.93-103
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• 2002

A new current mirror for high-accuracy current-mode signal processing and integrated circuit design was proposed. The current mirror adopts the technique of an adaptive feedback to reduce the input impedance and the output stage of regulated cascode current mirror to increase the output impedance. Simulation results show that the current mirror has input impedance of 0.9Ω, the output impedance of 415 MΩ, and current gain of 0.96 at the supply voltage Vcc=5V. The power dissipation is 1.5㎽. In order to certify the applicability of the proposed current mirror, a voltage-to-current converter using the current mirror is designed. Simulation results show that the converter has good agreement with theoretical equation and has three times better conversion characteristics when compared with voltage-to-current converter using Wilson current mirror.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.1
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• pp.13-20
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• 2001

In this appear, we proposed the new current mirror has large output resistance and excellent current matching characteristics. If supply voltage were lowered under the conventional CMOS operational amplifier, the wing of out put power could be restricted. So, the paper suggests a new way of differential operational amplifier circuit to solve the problem. The paper proposes that a new current mirror increases output swing and has a stable operation. We compare and verify characteristics of the proposed current mirror with the cascoded current mirror and the regulated current mirror through simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.54-59
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• 2008

A highly accurate wide swing BiCMOS cascode current mirror is proposed. It uses the base-current compensated BJT current mirror. It increases both output impedance and output voltage range by using the npn-NMOS cascode instead of the NMOS-NMOS cascode. The npn transistor copies the input current and the NMOS transistor increases the output impedance for the accurate current mirroring. The proposed current mirror achieves highly constant current for wide output voltage range. Simulation results were verified with measurements performed on a fabricated chip using a 5/16V 0.5um BCD process. It has only $-2.5%{\sim}1.0%$ current error for $0.3V{\sim}16V$ output voltage range.

• Proceedings of the KIEE Conference
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• 2006.04b
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• pp.256-257
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• 2006

전류 미러회로를 이용한 직류 전류 센서를 이용하면 간단하게 전류센서회로를 구성할 수 있다. 더우기 Shunt 저항에서 낮은 전압을 이용하므로 효율적인 전류감지회로를 구성할 수 있다. 그러나 트랜지스터의 에미터 베이스 전압을 이용하므로 비 직선성이 두드러진다. 이 회로의 전류센서, 온도특성등 여러 전기적 물리적 특성을 이해하고 이를 마이크로프로세서를 이용하여 그 특성을 상쇄하는 구성을 고려하여 보기로 한다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.6
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• pp.72-76
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• 2003

We developed a polarimetric fiber-optic current sensor using a length of twisted fiber and a Faraday rotator mirror which was used to suppress the linear birefringence effect. A gold coated mirror was also used as the sensor coil reflector, and the results were compared with the case of FRM. From the experimental results, it is clear that the FRM greatly enhances the stability of the fiber optic current sensor output..

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.79-85
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• 2009

In this paper, an accurate current reference using temperature and process compensation current mirror (TPC-CM) is proposed. The temperature independent reference current is generated by summing a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current. However, the temperature coefficient and magnitude of the reference current are influenced by the process variation. To calibrate the process variation, the proposed TPC-CM uses two binary weighted current mirrors which control the temperature coefficient and magnitude of the reference current. After the PTAT and CTAT current is measured, the switch codes of the TPC-CM is fixed in order that the magnitude of reference current is independent to temperature. And, the codes are stored in the non-volatile memory. In the simulation, the effect of the process variation is reduced to 0.52% from 19.7% after the calibration using a TPC-CM in chip-by-chip. A current reference chip is fabricated with a 3.3V 0.35um CMOS process. The measured calibrated reference current has 0.42% variation for $20^{\circ}$C${\sim}$100$^{\circ}$C.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.2
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• pp.333-338
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• 2008

In this paper, a new NMOS current-mirror type bridge rectifier for driving RFID chips, whose minimum input voltage required to obtain the effective DC output voltage is low enough and whose power dissipation can be reduced than that of conventional one, is proposed. The designed rectifier is able to supply high enough and well-rectified DC voltages to drive RFID transponder chips for the frequency range of 13.56 MHz HF(for ISO 18000-3), 915 MHz UHF(fur ISO 18000-6), and 2.45 GHz microwave(for ISO 18000-4). Output characteristics of the proposed rectifier are analyzed with the high frequency equivalent circuit. And the circuitry method for effective reducing of the gate leakage current due to the increasing of operating frequency is also proposed theoretically. Using this method, the power consumption of $100\;{\mu}W$ and the DC output voltage of 2.13V for 3V peak-to-peak input voltage and $45\;K{\Omega}$ load resistance are obtained. Compared to conventional one, the proposed rectifier operates in more stable and shows superior characteristics in UHF and microwave frequencies.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.201-210
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• 2002

This paper describes a 3.3 (V) low power 4 digit CMOS quaternary to analog converter (QAC) designed with a neuron MOS($\upsilon$MOS) down literal circuit block and cascode current mirror source block. The neuron MOS down literal architecture allows the designed QAC to accept not only 4 level voltage inputs, but also a high speed sampling rate quaternary voltage source LSB. Fast settling time and low power consumption of the QAC are achieved by utilizing the proposed architecture. The simulation results of the designed 4 digit QAC show a sampling rate of 6(MHz) and a power dissipation of 24.5 (mW) with a single power supply of 3.3 (V) for a CMOS 0.35${\mu}{\textrm}{m}$ n-well technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.754-764
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• 2001

Class A bipolar second-generation current conveyor (CCII) with low current-input impedance and its offset-compensated CCII for high-accuracy current-mode signal processing are proposed. The CCIIs consist of a regulated current-cell for current input, a emitter follower for voltage input, and a cascode current mirror lot current output. In these architecture, the two input stages are coupled by current mirror to reduce the current input impedance. Experiments show that the CCII has impedance of 8.4 Ω and offset voltage of 40 mV at current input terminal. To reduce this offset, the offset-compensated CCII adopts diode-connected npn and pnp transistor in the proposed CCII. Experiments show that the offset-compensated CCII has current input impedance of 2.1 Ω and offset voltage of 0.05 mV. The 3-dB cutoff frequency of the CCIIs when used as a voltage follower extends beyond 30 MHz. The power dissipation is 7.0 mW

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.82-90
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• 2011

A novel class AB current subtracter(CS) and its application to Norton amplifier(NA) for low-power current-mode signal processing are designed. The CS is composed of a translinear cell, two current mirrors, and two common-emitter(CB) amplifiers. The principle of the current subtraction is that the difference of two input current applied translinear cell get from the current mirror, and then the current amplify through CB amplifier with ${\beta}$ times. The NA is consisted of the CS and wideband voltage buffer. The simulation results show that the CS has current input impedance of $20{\Omega}$, current gain of 50, and current input range of $i_{IN1}$ > $i_{IN2}{\geq}4I_B$. The NA has unit gain frequency of 312 MHz, transresistance of 130 dB, and power dissipation of 4mW at ${\pm}2.5V$ supply voltage.