• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.170-172
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• 2007

본 논문은 optocoupler를 사용하여 궤환단을 절연한 오프라인 플라이백 변환기의 설계와 해석에 중점적인 목적을 두었으며, 부가적으로 궤환단을 절연하지 않은 구조를 가지는 전류모드제어 플라이백변환기와 optocoupler로 궤환단을 절연한 구조를 가지는 전류모드제어 플라이백 변환기의 상관관계를 분석하였다. 설계와 해석을 하기 위해 PSIM 시뮬레이터를 사용하여 PSIM 모델을 제시하였으며, 제시한 PSIM 모델은 110$\sim$220V 오프라인 전원을 입력하여 10V/5A의 출력을 가지는 50W 오프라인 전류모드 플라이백 변환기의 설계와 실험을 통하여 높은 정확성과 사용의 용이성을 확인하였다.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1556-1557
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• 2007

LCD BLU에 광원의 수명을 측정하고, 고장모드를 분석하기 위해서는 광원을 구성하고 있는 각각의 성분 중에서 광원 자체를 구성하고 있는 R/G/B 광원에 대한 Burn-in test 및 고장모드를 분석하였다. LCD BLU에 있어서 R/G/B LED광원의 역할은 BLU 자체의 수명과 성능에 가장 큰 영향을 미친다. 서로 각각 사용조건하에서의 수명과 성능의 차이에 따라서 BLU 자체의 수명이 결정된다. 이를 평가가기 위해 LED device에 대한 가속수명테스트를 위한 Burn-in test를 실시하였으며, 발생한 고장모드를 분석하였다. 분석결과 누설전류 증가로 인한 불량이 주로 발생하였다. 누설전류 증가를 평가하기 위해 Photo emission microscope(PHEMOS-1000, MoDooTEK Inc.)을 이용하여 저전류에서의 LED chip의 누설전류에 의한 발광을 관찰함으로 인해, LED chip의 신뢰성 및 평가 기준이 됨을 알 수 있다.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1080-1082
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• 2000

본 연구에서는 부하의 급격한 변화 또는 병렬컨버터를 구성하는 단위컨버터의 고장 발생 시 안정적인 병렬컨버터의 운용을 위한 연구를 수행하였다. 단 위컨버터는 응답특성을 개선하기 위하여 평균전류모드제어를 채택하였으며, 병렬컨버터의 부하전류분담을 위하여 최대전류 제어법을 이용하였다. 병렬컨버터의 모델을 도출하여 부하전류분담 제어에 따른 동작특성을 분석하였다. 급격한 부하변화와 단위컨버터의 고장발생 시 안정된 병렬컨버터의 특성을 실험을 통하여 확인하였다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.12
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• pp.157-163
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• 2008

In the multi-phase interleaved converter with peak current mode control, current imbalance is measured when inductors of converter module are not exactly identical. In this paper current-sharing controller is proposed to balance phase current of converter modules. It also is designed to have good transient response. Proposed method implemented the 2-phase and 4-phase interleaved boost converter with imbalanced inductance. Experimental results verify the performance of Current share during the transient state of converter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.5
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• pp.1117-1125
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• 2000

A current mode PWM method applied one cycle response to averaging circuit model Buck converters is presented. The controller nonlinear PWM implement is based on the error between the switched variable and the response reference to zero each cycle. As the result, the system transfer function is derived as a function of the desired close loop poles, simplifying the design procedure and bringing forward all the important characteristics of the close loop system. The proposed controller has significant advantages over conventional current mode control methods in noise susceptibility, dynamic response and without inductor current sensing, Finally, the simulation and experiment results confirm the proposed PWM control techniques.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.1760-1762
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• 2010

본 논문에서 3치가산기와 승산기(multiplier)는 전류모드 CMOS에 의해서 구현된다. 첫째, 3치 T-gate를 집적회로 설계의 유효 가용성을 갖고 있는 전류모드 CMOS를 이용하여 구현한다. 둘째, 3치 T-gates를 이용해 회로가 유한체 GF (3)에 대하여 2변수 3치 가산표 (2-variable ternary addition table) 및 구구표 (multiplication table)가 실현되도록 구현한다. 마지막으로, 이러한 동작 회로들은 1.5 CMOS 표준 기술과 $15{\mu}A$ 단위전류(unit current) 및 3.3V 소스 전압 (VDD voltage)에 의해 활성화 된다. 활성화 결과는 만족할 만한 전류 특성을 나타냈다. 전류 모드 CMOS에 의하여 실행되는 3치가산기 및 승산기는 단순하며 와이어 라우팅(wire routing)에 대하여 정규적이고, 또한 셀 배열 (cell array)과 함께 모듈성 (modularity)의 특성을 갖고 있다.

• Korean Journal of Optics and Photonics
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• v.14 no.5
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• pp.521-529
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• 2003

For complex-coupled (CC) DFB lasers, we found that there might be little correlation between the single mode yields at threshold and above threshold. At threshold, the single mode yield considering f number of in-phase (IP) CC DFB lasers is the same as that of anti-phase (AP) CC DFB lasers. However, the single mode yield as a function of injection current above threshold of IP CC DFB lasers is much different from that of AP CC DFB lasers. In the case of IP CC DFB lasers, the single mode yield increases as the coupling coefficient ratio (CR) increases, while, in the case of AP CC DFB lasers, the single mode yield decreases rapidly regardless of CR as the injection current increases. In the case of AR-HR combinations, the effect of AR ref1ectivity on the single mode yield increases as the coupling strength decreases. As the coupling strength decreases, the CR at which the increase rate of the single mode yield starts to decrease, increases, and the maximum single mode yield increases. Single mode yields of AR-HR and AR-AR combinations are larger than those of AR-CL and CL-CL combinations.

• The KIPS Transactions:PartA
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• v.17A no.3
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• pp.121-126
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• 2010

This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.3
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• pp.479-486
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• 2020

In this paper, we present a design method for improving the linearity and dynamic range of the analog current mode multiplier circuit, which is one of the key devices in an analog current mode AI processor. The proposed circuit consists of 4 quadrant translinear loops made up of NMOS transistors only, which minimizes physical mismatches of the transistors. The proposed circuit can be implemented at 117㎛ × 109㎛ in 0.35㎛ CMOS process and has a total harmonic distortion of 0.3%. The proposed analog current mode multiplier is expected to be useful as the core circuit of a current mode AI processor.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.5
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• pp.443-450
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• 2000

A PWM inverter for an induction motor often has a problem with a high frequency leakage current that flows through stray capacitors between stator windings and a motor frame to ground. This paper proposes a new type of Active Common Mode Voltage Canceler circuit for the reduction of common mode voltage and high frequency leakage current generated by the PWM VSI-fed induction motor drives. The compensating voltage applied by the common made voltage canceler has the same amplitude as, hut the opposite polarity to, the common mode voltage by PWM Inverter. Therefore, common mode voltage and high frequency leakage current can be canceled. The proposed circuit consists of four-level half-bridge inverter and common-mode transformer. Simulated and experimental results show that common mode voltage canceler makes significant contributions to reducing a high frequency leakage current.