• Title/Summary/Keyword: 전류 드리프트

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Drift Self-compensating type Flux-meter Using Digital Sample and Hold Amplifier (Digital Sample and Hold 증폭기를 사용한 드리프트 자체 보상형 자속계의 제작)

  • Ka, Eun-Mie;Son, De-Rac
    • Journal of the Korean Magnetics Society
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    • v.15 no.6
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    • pp.332-335
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    • 2005
  • Output voltage of the flux-meter has always drift due to the input bias current of non-ideal operational amplifier. In this study we have employed a digital sample and hold amplifier which has no voltage drop to compensate drift of the flux-meter automatically. The drift of the developed flux-meter was smaller than $5{\times}10^{-8}\;Wb/s$ for the integration time constant of $RC=10^{-3}$ s.

Performance of Differential Field Effect Transistors with Porous Gate Metal for Humidity Sensors

  • Lee, Sung-Pil;Chowdhury, Shaestagir
    • Journal of Sensor Science and Technology
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    • v.8 no.6
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    • pp.434-439
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    • 1999
  • Differential field effect transistors with double gate metal for integrated humidity sensors have been fabricated and the drain current drift characteristics to relative humidity have been investigated. The aspect ratio was 250/50 for both transistors to get the current difference between the sensing device and non-sensing one. The normalized drain current of the fabricated humidity sensitive field effect transistors increases from 0.12 to 0.3, as relative humidity increases from 30% to 90%.

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The Discretization Method of the Stationary Drift-Diffusion Equation with the Fermi-Dirac Statistics (정상상태에서 Fermi 분포를 고려한 드리프트-확산 방정식의 이산화 알고리즘)

  • 이은구;강성수;이동렬;노영준;김철성
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.157-160
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    • 2001
  • 소자 내부의 전위와 전자 및 정공 의사 페르미 준위에 따른 반송자의 정확한 농도를 얻기 위해 Fermi-Dirac통계를 구현하는 방법을 제시하였다. 또한 Fermi-Dirac통계를 고려하여 반도체 방정식을 이산화하는 방법을 제안한다. 제안된 방법을 검증하기 위해 전력 바이폴라 접합 트랜지스터를 제작하였으며 모의 실험 결과 컬렉터-에미터 전압 대 컬렉터 전류는 현재 업계에서 상용화된 소자의 실측치와 비교하여 최대 15%이내의 상대오차를 보였다.

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Determination of optimal ion implantation conditions to prevent double snapback of high voltage operating DDDNMOS device for ESD protection (고전압 정전기 보호용 DDDNMOS 소자의 더블 스냅백 방지를 위한 최적의 이온주입 조건 결정)

  • Seo, Yong-Jin
    • Journal of IKEEE
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    • v.26 no.3
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    • pp.333-340
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    • 2022
  • Process and device simulations were performed to determine the optimal ion implantation conditions to prevent double snapback of high voltage operating DDDNMOS (double diffused drain N-type MOSFET) device for ESD protection. By examining the effects of HP-Well, N- drift and N+ drain ion implantation on the double snapback and avalanche breakdown voltages, it was possible to prevent double snapback and improve the electrostatic protection performance. If the ion implantation concentration of the N- drift region rather than the HP-Well region is optimally designed, it prevents the transition from the primary on-state to the secondary on-state, so that relatively good ESD protection performance can be obtained. Since the concentration of the N- drift region affects the leakage current and the avalanche breakdown voltage, in the case of a process technology with an operating voltage greater than 30V, a new structure such as DPS or colligation of optimal process conditions can be applied. In this case, improved ESD protection performance can be realized.

Current-Voltage Characteristics of Schottky Barrier SOI nMOS and pMOS at Elevated Temperature (고온에서 Schottky Barier SOI nMOS 및 pMOS의 전류-전압 특성)

  • Ka, Dae-Hyun;Cho, Won-Ju;Yu, Chong-Gun;Park, Jong-Tae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.4
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    • pp.21-27
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    • 2009
  • In this work, Er-silicided SB-SOI nMOSFET and Pt-silicided SB-SOI pMOSFET have been fabricated to investigate the current-voltage characteristics of Schottky barrier SOI nMOS and pMOS at elevated temperature. The dominant current transport mechanism of SB nMOS and pMOS is discussed using the measurement results of the temperature dependence of drain current with gate voltages. It is observed that the drain current increases with the increase of operating temperature at low gate voltage due to the increase of thermal emission and tunneling current. But the drain current is decreased at high gate voltage due to the decrease of the drift current. It is observed that the ON/Off current ratio is decreased due to the increased tunneling current from the drain to channel region although the ON current is increased at elevated temperature. The threshold voltage variation with temperature is smaller and the subthreshold swing is larger in SB-SOI nMOS and pMOS than in SOI devices or in bulk MOSFETs.

Characteristics Improvement of a FET-Type Glucose Sensor and Its Application to a Glucose Meter (FET형 포도당센서의 특성개선과 이를 이용한 포도당측정기 개발)

  • Lee, C.H.;Choi, S.B.;Lee, Y.C.;Seo, H.I.;Sohn, B.K.
    • Journal of Sensor Science and Technology
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    • v.7 no.4
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    • pp.271-278
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    • 1998
  • A ISFET-based glucose sensor has inherent problems such as low sensitivity, drift effect and long response time. For that reason, a amperometric actuation technique was introduce to make a highly sensitivity of the ISFET glucose sensor with a Pt actuator, which electrolyzes $H_2O_2$, one of the by a by-products of the oxidation reaction of glucose. Moreover, a potential-step measurement method detecting response by only the electrolysis of $H_2O_2$ was developed for eliminating a drift problem. The operation characteristics of ISFET-based glucose sensor was improved by using the amperometric actuation and a measurement techniques. The fabricated ISFET glucose sensor is shown good operation such as characteristics(30mM PBS, about 26mV/decade) and linearity. A portable glucose meter with a highly resolution by using the fabricated ISFET-based glucose sensor with Pt actuation was developed and its characteristics investigated.

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Design of Compensated Digital Interface Circuits for Capacitive Pressure Sensor (용량형 압력센서용 디지탈 보상 인터페이스 회로설계)

  • Lee, Youn-Hee;Sawada, Kouji;Seo, Hee-Don;Choi, Se-Gon
    • Journal of Sensor Science and Technology
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    • v.5 no.5
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    • pp.63-68
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    • 1996
  • In order to implement the integrated capacitive pressure sensors, which contains integrated interface circuits to detect the electrical output signal, several main factors that have a bad effect on the characteristics of sensors must be improved, such as parasitic capacitance effects, temperature/thermal drift, and the leakage current of a readout circuitry. This paper describes the novel design of the dedicated CMOS readout circuitry that is consists of two capacitance to frequency converters and 4 bit digital logic compensating circuits. Dividing the oscillation frequency of a sensing sensor by that of reference sensor, this circuit is designed to eliminate the thermal/temperature drift and the effect of the leakage currents, and to access a digital signals to obtain a high signal-to-noise(S/N)ratio. Therefore, the resolution of this circuit can be increased by increasing the number of the digital bits. Digital compensated circuits of this circuits, except for the C-F converters, are fabricated on a FPGA chip, and fundamental performance of the circuits are evaluated.

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Two-Dimensional Numerical Simulation of GaAs MESFET Using Control Volume Formulation Method (Control Volume Formulation Method를 사용한 GaAs MESFET의 2차원 수치해석)

  • Son, Sang-Hee;Park, Kwang-Mean;Park, Hyung-Moo;Kim, Han-Gu;Kim, Hyeong-Rae;Park, Jang-Woo;Kwack, Kae-Dal
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.1
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    • pp.48-61
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    • 1989
  • In this paper, two-dimensional numerical simulation of GaAs MESFFT with 0.7${\mu}m$ gate length is perfomed. Drift-diffusion model which consider that mobility is a function of local electric field, is used. As a discretization method, instead of FDM (finite difference method) and FEM (finite element method), the Control-Volume Formulation (CVF) is used and as a numerical scheme current hybrid scheme or upwind scheme is replaced by power-law scheme which is very approximate to exponential scheme. In the process of numerical analysis, Peclet number which represents the velocity ratio of drift and diffusion, is introduced. And using this concept a current equation which consider numerical scheme at the interface of control volume, is proposed. The I-V characteristics using the model and numerical method has a good agreement with that of previous paper by others. Therefore, it is confined that it may be useful as a simulator for GaAs MESFET. Besides I-V characteristics, the mechanism of both velocity saturation in drift-diffusion model is described from the view of velocity and electric field distribution at the bottom of the channel. In addition, the relationship between the mechanism and position of dipole and drain current, are described.

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Improved Stability of GaN-based Hydrogen Sensor with SnO2 Nanoparticles/Pd Catalyst Layer Using UV Illumination (자외선 조사를 이용한 SnO2 나노입자/Pd 촉매층을 갖는 GaN 기반 수소 센서의 안정성 개선 연구)

  • Won-Tae Choi;Hee-Jae Oh;Jung-Jin Kim;Ho-Young Cha
    • Transactions on Semiconductor Engineering
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    • v.1 no.1
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    • pp.9-13
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    • 2023
  • An AlGaN/GaN heterojunction-based hydrogen sensor with SnO2 nanoparticles/Pd catalyst layer was fabricated for room-temperature hydrogen detection. The fabricated sensor exhibited unstable drift in standby current when it was operated at room temperature. The instability in the sensing signal was dramatically improved when the sensor was operated under UV illumination.

Study on Integrated for Capacitive Pressure Sensor (용량성 압력센서의 집적화에 관한 연구)

  • 이윤희
    • Journal of the Korean Institute of Telematics and Electronics T
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    • v.35T no.1
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    • pp.48-58
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    • 1998
  • For the purpose of designing novel capacitance pressure sensor, several effects on sensitivity such as parasitic capacitance effects, temperature/thermal drift and leakage current have to be eleiminated. This paper proposed the experimental studies on frequency compensation method by electronic circuit technique, C-V converting method with switched capacitor and C-F converting method with schmitt trigger circuit. The third interface circuit by frequency compensation method is composed to eliminate the drift and leakage component by comparision sensing frequency with reference frequency. The signal transmission is realized by digital signal to minimize the influence of noise and high resolution is obtained by means of increasing the number of digital bits. In the fabricated high performance C-V interface, the offset voltage was not appeared, and in case of voltage source, 4.0V, feed back capacitance, 10㎊, the pressure, 0~10 ㎪, the sensitivity of C-V converter is 28 ㎷/㎪.V, the temperature drift characteristic, 0.051 %F.S./$^{\circ}C$ and C-F converter shows -6.6 Hz/pa, 0.078 %F.S./$^{\circ}C$ respectively, relatively good ones.

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