• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.9
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• pp.4186-4192
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• 2012

Because wind turbines are larger and more off-shore construction due to economic and environmental factors, it is more difficult to access the wind turbine as well as the necessary parts and the maintenance costs are increasing. So, we need to minimize fault elements and to prevent a secondary accident at failure through monitoring to reduce maintenance costs and to increase reliability of operation. In this paper we have implemented ZigBee based wireless sensor nodes and network for wind turbine condition monitoring using temperature, humidity, voltage, current, wind direction, and wind speed sensors. ZigBee wireless sensor nodes signals are transmitted to a central monitoring system via routers. Also, the sensor signals are collected and processed using LabVIEW program to monitor the wind turbine conveniently. The administrators and users can monitor the condition of wind turbine at remote site in real time over TCP/IP.

• Journal of Satellite, Information and Communications
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• v.11 no.3
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• pp.24-27
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• 2016

In this study, a 1kW Solid Oxide Fuel Cell(SOFC) test system was developed. A SOFC is the most promising power system to provide the higher efficient(over 50%) for house application area(1~10kW). To develop the optimized test system, the temperature control module that controls the preprocess and reaction condition, the flow control module that controls of the mass of reactants, and the electric loader that tests the discharge performance condition, etc. The temperature control module was designed to provide the high control resolution(under $1^{\circ}C$ at $750^{\circ}C$ of operating temperature) using K-type thermal couple. The flow control module was designed control blower and heater precisely using the phase control method. And the electric loader is designed that provide CV, CC, CR discharge mode and minimized the operating error adopting the independent DC-DC converter on analog input and output module. The performance of the developed SOFC test system showed that the accuracy of stack voltage was 0.15% at 80V and stack current was 0.1% at 100A.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2708-2715
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• 2012

This paper proposes a new sensorless speed control scheme of induction motor using Model Reference Adaptive Control and Direct Torque Control System. The Model Reference Adaptive Control System is based on the comparison between the outputs of Reference Model and Adjustable Model. The error between the estimated quantities obtained by the two models is used to drive a suitable adaptation mechanism which generates the estimated rotor speed for the Adjustable Model. And the Direct Torque Control scheme controls torque and flux by restricting the flux and torque errors within respective hysteresis bands, and motor torque and flux are controlled by the stator voltage space vector using optimum inverter switching table. The simulation results of proposed method indicate good speed responses from the low speed range to the high, and also show favorable characteristics of load operation.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2000.05a
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• pp.51-52
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• 2000

전기아연도금강판은 표면이 미려하고 희생방식력이 뛰어나기 때문에 주로 자동차와 가전, 건자재 등에 많이 사용된다. 현재 냉연 표면처리 제품들은 연속도금공정에 의해 생산되고 있으며 고전류밀도에 의한 고속생산과 도늠액 제조와 조성이 비교적 단순해야 하는 여러 가지 이유로 염산욕과 황산욕을 가장 많이 사용하고 있다. 최근에 신설된 당사의 전기도금공정은 수직형으로 황산욕에서 불용성 양극을 채용하여 아연을 전기도금하고 있다. 일반적으로 황산욕은 염산욕 대비 전기 전도성이 나빠 과전압이 크게 걸리므로 불용성 양극을 사용하여 극간 거리를 최소화할 필요가 있다. 그러나 $Ir0_2$가 코팅된 불용성 양극은 가격이 비싸기 때문에 극간 거리를 너무 짧게 하면 깡대에 의해 손상을 받을 수가 있어 극간 거리를 줄이는데 한제가 있다. 따리서 용액의 전도도들 증가시켜 과전합을 줄이기 위해서는 타사에서 현재 사용하고 있는 황산나트륨, 황산칼륨, 황산암모늄 등에 대한 검토가 필요하다. 전기전도 보조제들은 용액의 전기전도도 뿐만 아니라 도금층의 외관 및 미세구조에도 많은 영향을 주는 것으로 알려져 있다. 따라서 본 연구에서는 황산나트륨, 황산암모늄의 농도를 변화시켜 표면외관, 한계전류밀도, 미세구조, 우선배향성 등을 조사하여 최적의 물성을 갖는 아연 도금층을 얻기 위한 조건을 도출하고자 하였다. 전기아연도금용 소재로는 두께 0.8mm이고 크기가 $100{\times}120mm$인 중저탄소강 (0.02% C)을 사용하였으며 전처리 과정으로 탈지와 산세를 행하고 현장 도금액을 사용하여 다음과 같은 조건 하에서 아연도금을 행하였고 극간전합을 측정하였다. 도금 후 표면의 미세구조는 SEM을 사용하여 관찰하였으며 표면외관 특성을 분석하기 위해 광택도계(Tri- Microgloss-60-85)를 이용하여 입사각 $60^{\circ}$ 에서 광택도를 측정하였고, 색차계(Color Quest II Hunter Lab.)를 사용하여 백색도를 각각 측정하였다. 또한 X선 회절기를 이용하여 도금층의 우선 배향성을 분석하였다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.8-16
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• 1999

This paper presents a new simulation-based analog cell synthesis approach with improved simulation efficiency For the hierarchical synthesis of analog cells we developed the sub-circuit optimizers such as current mirror and differential input stage. Each sub-circuit optimizer can be used for synthesis of analog cells such as OTA(operational transconductance amplifier), 2-stage OP-AMP and comparator. To reduce the time spending of the simulation-based synthesis we propose 2-stage searching scheme and simulation data reusing scheme. With those schemes the synthesis time spending of OTA was reduced from 301.05sec to 56.52sec by 81.12%. Since our synthesis system doesn't need other additional physical parameters except SPICE parameters, and is independent of the process and its model level, the time spending to port to other process is minimized. We synthesized OTA and 2-stage OP-AMP respectively with our approach to show its usefulness.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.49-58
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• 2014

A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.15-23
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• 2007

This paper describes a dual frequency synthesizer designed in a 0.2$\mu$m CMOS technology for wireless LAN applications. The design is focused mainly on low-power characteristics. Power dissipation is minimized especially in VCO and prescaler design. The designed synthesizer includes all building blocks for elimination of external components, other than the crystal. Its operating frequency can be programmed by external data. It operates in the frequency range of 2.3GHz to 2.7GHz (RF) and 250MHz to 800MHz (IF) and consumes 5.14mA at 2.5GHz and 1.08mA at 0.5GHz from a 2.5V supply. The measured phase noise is -85dBc/Hz in-band and -105dBc/Hz at 1MHz offset at IF band. The die area is 1.7mm$\times$1.7mm.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.69-76
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• 2007

This paper presents the design of LVDS (Low-Voltage-Differential-Signaling) transmitter for Gb/s-per-pin operation. The proposed LVDS transmitter is designed using BiCMOS technology, which can be compatible with CMOS technology. To reduce chip area and enhance the robustness of LVDS transmitter, the MOS switches of transmitter are replaced with lateral bipolar transistor. The common emitter current gain($\beta$) of designed bipolar transistor is 20 and the cell size of LVDS transmitter is $0.01mm^2$. Also the proposed LVDS driver is operated at 1.8V and the maximum data rate is 2.8Gb/s approximately In addition, a novel ESD protection circuit is designed to protect the ESD phenomenon. This structure has low latch-up phenomenon by using turn on/off character of P-channel MOSFET and low triggering voltage by N-channel MOSFET in the SCR structure. The triggering voltage and holding voltage are simulated to 2.2V, 1.1V respectively.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.65-69
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• 2012

Composite coating can be manufactured during the electroplating with the bath containing a suspension of particles: ceramic, polymer, nanopowders. Improvement of hardness, wear resistance, corrosion resistance and lubrication properties are well-known advantage of composite coating. In this study, nano $TiO_2$ powder dispersed Ni composite plating was investigated. The improvement of surface hardness and photo decomposition effects can be expected in this coating. Zeta potential was measured with pH. The effect of ultrasonication time and types of ultrasonicator were studied to minimize the agglomeration of $TiO_2$ nanopowders in the electrolyte. Optimum conditions for nano $TiO_2$ dispersed Ni composite coating were $40mA/cm^2$ of current density, pH 3.5, and $50^{\circ}C$. At these conditions, $TiO_2$ nanoparticles contents in the Ni deposit was 15-20 at.%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.71-77
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• 2009

A novel phase-locked loop(PLL) architecture with multiple charge pumps for fast locking has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. The fast locking PLL that changes its loop bandwidth through controlling charge pumps depending on locking status has been designed. The capacitor usually occupying the larger portion of the chip is also minimized with the proposed scheme. Therefore, the PLL size of $990{\mu}m\;{\times}\;670{\mu}m$ including resistors and capacitors at the bandwidth of 29.9KHz has been achieved. It has been fabricated with 3.3V $0.35{\mu}m$ CMOS process. The locking time is less than $6{\mu}s$ with the measured phase noise of -90.45dBc/Hz @1MHz at 851.2MHz output frequency.