• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.5 s.347
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• pp.35-44
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• 2006

Reflective semiconductor optical amplifiers(R-SOAs) were designed with high gain, wide optical bandwidth, high thermal reliability and wide modulation bandwidth in TO-can package for the transmitter of wavelength division multiplexed-passive optical network(WDM-PON) application. Double trench structure and current block layer were introduced in designing the active layer of R-SOA to enable high speed modulation. The injection power requirement and the viable temperature range of WDM-PON system are experimentally analysed in based on Amplified Spontaneous Emission(ASE)-injected R-SOAs. The effect of the different injection spectrum in the gain-saturated R-SOA was experimentally characterized based on the measurements of excessive intensity noise, Q factor, and BER. The proposed spectral pre-composition method reduces the bandwidth of injection source below the AWG bandwidth and thereby avoids spectrum distortion impeding the intensity noise reduction originated from the amplitude squeezing.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.10 s.352
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• pp.90-97
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• 2006

We report our research work on the millimeter-wave broadband amplifier integrating the shunt peaking technology with the cascode configuration. The millimeter-wave broadband cascode amplifier on MIMIC technology was designed and fabricated using $0.1{\mu}m\;{\Gamma}-gate$ GaAs PHEMT, CPW, and passive library. The fabricated PHEMT has shown a transconductance of 346.3 mS/mm, a current gain cut off frequency ($f_T$) of 113 GHz, and a maximum oscillation frequency ($f_{max}$) of 180 GHz. To prevent oscillation of designed cascode amplifier, a parallel resistor and capacitor were connected to drain of common-gate device. For expansion of the bandwidth and flatness of the gain, we inserted the short stub into bias circuits and the compensation transmission line between common-source device and common-gate device, and then their lengths were optimized. Also, the input and output stages were designed using the matching method to obtain the broadband characteristic. From the measurement, we could confirm to extend bandwidth and flat gain by integrating the shunt peaking technology with the cascode configuration. The cascode amplifier shows the broadband characteristic from 19 GHz to 53.5 GHz. Also, the average gain of this amplifier is about 6.5 dB over the bandwidth.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1169-1176
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• 2010

The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.678-684
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• 2013

This paper describes a low-power baseband circuit for SAW-less LTE-Advanced transmitters. The proposed transmitter baseband circuit consists of a 2nd-order Tow-Thomas type active RC-LPF and a 1st-order passive RC LPF. It can provide a 7 multi-channel cut-off frequencies and wide gain control range of -41 dB ~ 0 dB with a 1-dB step. The proposed 2nd-order active RC-LPF adopts an op-amp in which three other sub-op amps are in parallel connected to reduce DC current for different cutoff frequency. In addition, each sub-op amp adopts both Miller and feed-forward phase compensation method to achieve an UGBW of more than 1-GHz with a small DC power consumption. The proposed baseband circuit is implemented in 65-nm CMOS technology, consuming DC power from 6.3 mW to 24.1 mW from a 1.2V supply voltage for each different cut-off frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.11 s.114
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• pp.1021-1029
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• 2006

In this paper, we designed and implemented a dual wideband dipole type antenna for the reception of S-DMB (Satellite Digital Multimedia Broadcasting) and 2.4/5 GHz WLAN(Wireless Local Area Network) signals. The proposed antenna based on conventional monopole type dual band antenna was implemented as planar wideband dipole type antenna with the volume of $8{\times}33.8{\times}1.68mm^3$. The proposed antenna is printed type on FR4 substrate of 1.6 mm thick and composed of a dipole type antenna for low frequency band and two symmetric structured resonance elements for high frequency band. We confirmed antenna area with dense surface current for each frequency band with simulation. By varying the length of the antenna area with dense surface current, we could vary resonance frequency of each frequency band separately. Impedance bandwidths$(VSWR{\leq}2)$ are 362 MHz(14.23 %) for 2 GHz band and 1188 MHz(22.13, %) for 5 GHz band which show wideband characteristic. Measured maximum gains were 4.33 dBi for 2 GHz band and 5.48 dBi for 5 GHz band which showed improved performance. And the implemented antenna has a good omni-directional radiation pattern characteristic.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.2
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• pp.139-145
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• 2024

This paper presents the design of a voltage controlled oscillator (VCO) which is one of the key building blocks in modern wireless communication systems with small VCO gain (K_vco) variation. To compensate conventional large K_vco variation, a series varactor bank has been added to the conventional LC-tank with parallel capacitor bank array. And also, in order to achieve excellent phase noise performance while maintaining wide tuning range, a mixed coarse/fine tuning scheme(series varactor array and parallel capacitor array) is chosen. The switched varactor array bank is controlled by the same digital code for switched capacitor array without additional digital circuits. For use at a low voltage of 1.2V, the proposed current reference circuit in this paper used a current reference circuit for safety with the common gate removed more safely. Implemented in a TSMC 0.13㎛ CMOS RF technology, the proposed VCO can be tuned from 4.4GH to 5.3GHz with the K_vco (VCO gain ) variation of less than 9.6%. While consuming 3.1mA from a 1.2V supply, the VCO has -120dBc/Hz phase noise at 1MHz offset from the carrier of the 5.3 GHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.902-911
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• 2003

Using InGaP/GaAs HBT power cells with a 2.0${\times}$20$\mu\textrm{m}$$^2$ emitter area of a unit HBT, a two stage MMIC power amplifier has been developed for IMT-2000 handsets. An active-bias circuit has been used for temperature compensation and reduction in the idling current. Fitting on measured S-parameters of the HBT cells, circuit elements of HBT's nonlinear equivalent model have been extracted. The matching circuits have been designed basically with the extracted model. A two stage HBT MMIC power amplifier fabricated using ETRI's HBT process. The power amplifier produces an 1-㏈ compressed output power(P$\_$l-㏈/) of 28.4 ㏈m with 31% power added efficiency(PAE) and 23-㏈ power gain at 1.95 GHz in on-wafer measurement. Also, the power amplifier produces a 26 ㏈m output power, 28% PAE and a 22.3-㏈ power gain with a -40 ㏈c ACPR at a 3.84 ㎒ off-center frequency in COB measurement.quency in COB measurement.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.175-184
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• 2006

In this paper, we describe a 900MHz CMOS RF transceiver using an ISM band for ZigBee applications. The architecture of the designed rx front-end, which consists of a low noise amplifier, a down-mixer, a programmable gain amplifier and a band pass filter. And the tx front-end, which consists of a band pass filter, a programmable gain amplifier, an up-mixer and a drive amplifier. A low-if topology is adapted for transceiver architecture, and the total current consumption is reduced by using a low power topology. Entire transceiver is verified by means of post-layout simulation and is implemented in 0.18um RF CMOS technology. The fabricated chip demonstrate the measured results of -92dBm minimum rx input level and 0dBm maximum tx output level. Entire power consumption is 32mW(@1.8VDD). Die area is $2.3mm{\times}2.5mm$ including ESD protection diode pads.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.1-6
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• 2010

We present simulation results on DC characteristics of AlGaN/GaN HEMT having stair-type gate electrodes, in comparison with those of the conventional single gate AlGaN/GaN HEMTs and field-plate enhanced AlGaN/GaN HEMTs. In order to reduce the internal electric field near the gate electrode of conventional HEMT and thereby to increase their DC characteristics, we applied three-layered stacking electrode schemes to the standard AlGaN/GaN HEMT structure. As a result, we found that the internal electric field was decreased by 70% at the same drain bias condition and the transconductance (gm) was improved by 11.4% for the proposed stair-type gate AlGaN/GaN HEMT, compared with those of the conventional single gate and field-plate enhanced AlGaN/GaN HEMTs.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.66-70
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• 2016

This paper presents an 24 GHz I/Q LO generator for a heartbeat measurement radar system. In order to improve the mismatch performance between I and Q LO signals against process variation, a 24 GHz I/Q LO generator employing a low-pass phase shifter and a high-pass phase shifter composed of inductors and capacitors is proposed. The proposed 24 GHz I/Q LO generator consists of an LO buffer, a low-pass phase shifter and a high-pass phase shifter. It was designed using a 65 nm CMOS technology and draws 8 mA from a 1 V supply voltage. The proposed 24 GHz I/Q LO generator shows a gain of 7.5 dB, a noise figure of 2.3 dB, 0.1 dB gain mismatch and $4.3^{\circ}$ phase mismatch between I and Q-path against process and temperature variations for the operating frequencies from 24.05 GHz to 24.25 GHz.