• Journal of IKEEE
• /
• v.16 no.2
• /
• pp.131-137
• /
• 2012

This paper is study on a new high efficiency DC-DC converter of discontinuous conduction mode (DCM) with zero voltage switching (ZVS). The converters of high efficiency are generally made that the power loss of the used semiconductor switching devices is minimized. The proposed converter is accomplished that the turn-on operation of switches is on zero current switching (ZCS) by DCM. The converter is also applicable to a new quasi-resonant circuit to achieve high efficiency converter. The control switches using in the converter are operated with soft switching, that is, ZVS and ZCS by quasi-resonant method. The control switches are operated without increasing their voltage and current stresses by the soft switching technology. The result is that the switching loss is very low and the efficiency of the converter is high. The soft switching operation and the system efficiency of the proposed DCM-ZVS converter are verified by digital simulation and experimental results.

• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.48 no.8
• /
• pp.431-439
• /
• 1999

Among the variable-speed AC motor drive systems, the static slip power recovery system has been widely adopted in large power drives because a high efficiency drive can be obtained by recovering the slip power to the AC line. Although many improvements have been made in this system, several problems also remain such as the need of transformer in inverter AC side, which results in limiting speed control range and increasing the losses, production of reactive power by the control of inverter firing angle, harmonics in line currents, and so on. This paper presents the novel high performance slip power recovery system using the boost converter and small size filter in the rotor circuit, which recovers slip power of a wound rotor induction machine to AC supply efficiently with the aid of the boost converter, in which most of the problems in conventional system can be solved. The speed can be controlled by the duty ratio of the converter switch, not by inverter firing angle. As a results, the proposed system can operate in high power factor and the harmonic currents caused by the inverter and rectifier can be considerably suppressed. The validity of the proposed system verified by demonstrating the good agreement in the simulation and experimental results.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.14 no.1
• /
• pp.225-234
• /
• 2019

By using the Triboelectric nanogenerators, known as TENG, we can take advantages of high conversion efficiency and continuous power output even with small vibrating energy sources. Nonlinear energy extraction techniques for Triboelectric vibration energy harvesting usually requires synchronized active electronic switches in most electronic interface circuits. This study presents a nonlinear energy harvesting with high energy conversion efficiency to harvest and save energies from human active motions. Moreover, the proposed design can harvest and store energy from sway motions around different directions on a horizontal plane efficiently. Finally, we conducted a comparative analysis of a multi-mode energy storage board developed by a silicon-based piezoelectricity and a transparent TENG cell. As a result, the experiment showed power generation of about 49.2mW/count from theses multi-fully harvesting source with provision of stable energy storages.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.21 no.2
• /
• pp.137-142
• /
• 2021

A Photovoltaic power streetlight is a system that uses solar energy to charge a secondary battery and then uses it for night lighting through a lamp, and can be configured as a standalone or grid-connected type by installing an LED streetlight at the load end. The energy generated through the solar cell module can be charged to the secondary battery through the charge/discharge control device, and then the LED street light can be turned on and off by comparing the power generation voltage and the charging voltage according to the monitoring of solar radiation, or by setting a specific time after sunset or sunrise. Based on these contents, this paper designed and manufactured a simulated solar power streetlight for education using new and renewable energy utilization and storage functions. Using these educational equipment, students can 1) understand the flow of energy change using renewable energy including sunlight as electric energy, 2) understand new and renewable energy, and cultivate basic design and manufacturing application power of related products, 3) The use of new and renewable energy through power conversion and strengthening of practical training and analysis through hardware production can be instilled.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.3
• /
• pp.60-68
• /
• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.39 no.4
• /
• pp.16-24
• /
• 2002

This work describes a 10b 120 MSample/s CMOS pipelined A/D converter(ADC) based on a merged-capacitor switching(MCS) technique for high signal processing speed and high resolution. The proposed ADC adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area, and employs a MCS technique which improves sampling rate and resolution reducing the number of unit capacitor used in the multiplying digital-to-analog converter (MDAC). The proposed ADC is designed and implemented in a 0.25 um double-poly five-metal n-well CMOS technology. The measured differential and integral nonlinearities are within ${\pm}$0.40 LSB and ${\pm}$0.48 LSB, respectively. The prototype silicon exhibits the signal-to-noise-and-distortion ratio(SNDR) of 58 dB and 53 dB at 100 MSample/s and 120 MSample/s, respectively. The ADC maintains SNDR over 54 dB and the spurious-free dynamic range(SFDR) over 68 dB for input frequencies up to the Nyquist frequency at 100 MSample/s. The active chip area is 3.6 $mm^2$(＝ 1.8 mm ${\times}$ 2.0 mm) and the chip consumes 208 mW at 120 MSample/s.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.29 no.10
• /
• pp.758-765
• /
• 2018

This paper presents a 24-GHz frequency-modulated continuous wave(FMCW) radar transceiver with two Rx and one Tx channels in 65-nm complementary metal-oxide-semiconductor(CMOS) process and implemented it on a radar system using the developed transceiver chip. The transceiver chip includes a $14{\times}$ frequency multiplier, low-noise amplifier, down-conversion mixer, and power amplifier(PA). The transmitter achieves >10 dBm output power from 23.8 to 24.36 GHz and the phase noise is -97.3 GHz/Hz at a 1-MHz offset. The receiver achieves 25.2 dB conversion gain and output $P_{1dB}$ of -31.7 dBm. The transceiver consumes 295 mW of power and occupies an area of $1.63{\times}1.6mm^2$. The radar system is fabricated on a low-loss Duroid printed circuit board(PCB) stacked on the low-cost FR4 PCBs. The chip and antenna are placed on the Duroid PCB with interconnects and bias, gain blocks and FMCW signal-generating circuitry are mounted on the FR4 PCB. The transmit antenna is a $4{\times}4$ patch array with 14.76 dBi gain and receiving antennas are two $4{\times}2$ patch antennas with a gain of 11.77 dBi. The operation of the radar is evaluated and confirmed by detecting the range and azimuthal angle of the corner reflectors.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.21 no.9
• /
• pp.528-535
• /
• 2020

Recently, the protection coordination method of DC systems has been presented because renewable energy and distributed resources are being installed and operated in distribution systems. On the other hand, it is difficult to detect ground faults because there is no significant difference compared to a steady-state current in ungrounded IT systems, such as DC load networks and urban railways. Therefore, this paper formulates the detection principle of IMD (Insulation Monitoring Device) to use it as a protection coordination device in a DC system. Based on the signal injection method of IMD, which is analyzed by a wavelet transform, this paper presents an algorithm of detecting ground faults in a DC system in a fast and accurate manner. In addition, this paper modeled an IMD and an ungrounded DC system using the PSCAD/EMTDC S/W and performed numerical analysis of a wavelet transform with the Matlab S/W. The simulation results of a ground fault case in an ungrounded DC system showed that the proposed algorithm and modeling are useful and practical tools for detecting a ground fault in a DC system.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.306-306
• /
• 2008

기계적 에너지를 전기적 에너지로 변환하는 에너지 변환소자인 압전 세라믹스는 액추에이터, 변압기, 초음파모터, 초음파 소자 및 각종 센서로 응용되고 있으며, 그 응용분야는 크게 증가하고 있다. 최근에는 이러한 압전 소자를 앞으로 도래하는 ubiquitous, 무선 모바일 시대의 휴대용 전자제품, robotics, MEMS 분야 등의 대체 에너지원으로 응용하기 위한 연구가 진행되고 있다. 특히 인간의 걷기 운동 등과 같은 일상적인 동작으로 필요한 전력을 얻을 수 있고, 세라믹 소자를 이용하기 때문에 전자노이즈가 발생되지 않을 뿐 아니라 반영구적으로 사용할 수 가 있어서, 기존 이차전지를 대체 또는 보완 할 수 있는 방안도 검토되고 있다. PZT계 세라믹스는 높은 유전상수와 우수한 압전특성으로 전자세라믹스 분야에서 가장 널리 사용되어지고 있지만 $1200^{\circ}C$ 이상의 높은 소결온도 때문에 $1000^{\circ}C$ 부근에서 급격히 휘발되는 PbO로 인한 환경오염과 기본조성의 변화로 인한 압전 특성의 저하가 문제시 되고 있다. 또한 적층 세라믹스의 제작 시 구조적 특성상 내부전극이 도포된 상태에서 동시 소결이 필요한데, 융점이 낮은 Ag전극 대신 값비싼 Pd나 Pt가 다량 함유된 Ag/Pd, Ag/Pt 전극이 사용되고 있어 경제성이 떨어지는 단점을 갖게 된다. 순수 Ag 전극을 사용하거나 Ag의 비율이 높은 내부전극을 사용하기 위해서는 $900^{\circ}C$ 이하에서 소결되고 우수한 전기적 특성을 보이는 압전 세라믹스를 개발 하는 것이 필요하다. 따라서 본 연구에서는 압전특성이 우수한 $(Pb_{1-x}Cd_x)(Ni_{1/3}/Nb_{2/3})_{0.25}(Zr_{0.35}/Ti_{0.4})O_3$ 계의 조성을 설계하고, 소걸온도를 낮추기 위해서 2 단계 하소법을 이용하였다. 또한 $MnCO_3$, $SiO_2$, $Pb_3O_4$ 등을 소량 첨가하여 액상 소결 특성을 부여하여 소결 온도를 감소시키려는 시도도 하였다. 분말을 볼 밀링 (ball milling)을 통해 24시간 동안 혼합하고, 혼합된 분말은 $800^{\circ}C$에서 2시간 동안 하소하였다. 하소한 분말을 다시 72시간 동안 볼 밀링 하여 최종 분말을 얻었다. 최종 분말에 PVB를 첨가하여 직경 15mm의 디스크 형태로 성형한 후, 850~$975^{\circ}C$ 범위에서 온도를 변화시키면서 소결을 하였다. 최종 분말 및 소결된 시편을 XRD분석을 통하여 상을 확인하였고, SEM을 이용하여 미세조직을 관찰 하였다. 전기적 특성을 평가하기 위하여 두께를 1mm로 연마한 시편에 Ag 전극을 도포하여 $650^{\circ}C$에서 열처리한 후, 분극처리 하였다. 압전특성은 $d_{33}$-meter로 측정하였고, impedance analyzer를 이용하여 압전 특성 (전기기계결합계수 및 기계적품질계수)을 측정 하였다. 또한 강유전체 특성 평가 장치 (Precision-LC)를 이용하여 분극-전계 특성을 평가하였다. 이상의 연구를 통하여 소결 온도가 $900^{\circ}C$인 경우에서도 양호한 압전 특성을 확보 할 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.5 s.347
• /
• pp.54-63
• /
• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.