• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.34-41
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• 2011

This paper presents a 24 channel capacitive touch sensing ASIC. This ASIC consists of analog circuit part and digital circuit part. Analog circuits convert user screen touch into electrical signal and digital circuits represent this signal change as digital data. Digital circuit also has an I2C interface for operation parameter reconfiguration from host machine. This interface guarantees the stable operation of the ASIC even against wide operation condition change. This chip is implemented with 0.18 um CMOS process. Its area is about 3 $mm^2$ and power consumption is 5.3mW. A number of EDA tools from Cadence and Synopsys are used for chip design.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.57-66
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• 1999

This paper describes a 12b, 50 Msample/s CMOS AID converter using an acquisition-time minimization technique for the high-speed sampling rate of 50 MHz level. The proposed ADC is implemented in a $0.35\mu\textrm{m}$ double-poly five-metal n-well CMOS technology and adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area. The speed limitation of conventional pipelined ADCs comes from the finite bandwidth and resulting speed of residue amplifiers. The proposed acquisition-time minimization technique reduces the acquisition time of residue amplifiers and makes the waveform of amplifier outputs smooth by controlling the operating current of residue amplifiers. The simulated power consumption of the proposed ADC is 197 mW at 3 V with a 50 MHz sampling rate. The chip size including pads is $3.2mm\times3.6mm$.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.48-55
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• 1999

This paper describes automatic gain control circuit (AGC) design techniques for CMOS CCD camera interface systems. The required gain of the AGC in the proposed system is controlled directly by digital bits without conventional extra D/A converters and the signal settling behavior is almost independent of AGC gain variation at video speeds. A capacitor-segment combination technique to obtain large capacitance values considerably improves the effective bandwidth of the AGC based on switched-capacitor techniques. A proposed layout scheme for capacitor implementation shows AGC matching accuracy better than 0.1 %. The outputs from the AGC are transferred to a 10b A/D converter integrated on the same chip. The proposed AGC is implemented as a sub-block of a CCD camera interface system using a 0.5 um n-well CMOS process. The prototype shows the 32-dB AGC dynamic range in 1/8-dB steps with 173 mW at 3 V and 25 MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.6
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• pp.253-260
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• 2004

This paper proposes a novel algorithm for hybrid lossless audio coding, which employs an integer wavelet transform and a linear prediction model. The proposed algorithm divides the input signal into flames of a proper length, decorrelates the framed data using the integer wavelet transform and linear prediction and finally entropy-codes the frame data. In particular, the adaptive Golomb-Rice coding method used for the entropy coding selects an optimal option which gives the best compression efficiency. Since the proposed algorithm uses integer operations, it significantly improves the computation speed in comparison with an algorithm using real or floating-point operations. When the coding algorithm is implemented in hardware, the system complexity as well as the power consumption is remarkably reduced. Finally, because each frame is independently coded and is byte-aligned with respect to the frame header, it is convenient to move, search, and edit the coded, compressed data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.10-15
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• 2008

In this paper, a new NMOS gate cross-connected current-mirror type bridge rectifier for UHF RFID applications is presented. The DC converting characteristics of the proposed rectifier are analyzed with the high frequency equivalent circuit and the gate capacitance reduction technique for reducing the gate leakage current due to the increasing of operating frequency is also proposed theoretically by circuitry method. As the results, the proposed rectifier shows nearly same DC output voltages as the existing NMOS gate cross-connected rectifier, but it shows the gate leakage current reduced to less than 1/4 and the power consumption reduced more than 30% at the load resistor, and it shows more stable DC supply voltages for the valiance of load resistance. In addition, the proposed rectifier shows high enough and well-rectified DC voltages for the frequency range of 13.56MHz HF(for ISO 18000-3), 915MHz UHF(for ISO 18000-6), and 2.45 GHz microwave(for ISO 18000-4). Therefore, the proposed rectifier can be used as a general purpose one to drive RFID transponder chips on various RFID systems which use specified frequencies.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.4
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• pp.8-15
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• 2000

In this paper, we realize the active PFC(Power Factor Correction) system of BF(Boost Forward) converter with PWM-PFM(Pulse Width Modulation-Pulse Frequency Modulation) control technique to control DC output voltage, to remove the noise like harmonics at output voltage, and to control the input current with sinusoidal wave synchronized by the source voltage.To achieve the desired load voltage and improved PFC, we first implement current shaping control at the inverting stage and make the converted output DC voltage with forward converter. After making the ratio of output voltage to current as 50V/1A and the duty ratio greater than 0.5. When input voltage is 30V and boost inductance is 1.1mH. we control the voltage changing rate according to the variation of load resistance using a PWM-PFM control technique. And finally we prove experimentally, we attenuated its harmonics and improved PF up to 0.96 using the current shaping technique.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.4
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• pp.213-225
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• 2007

Flash memory is widely used as a storage device for potable equipments such as digital cameras, MP3 players and cellular phones because of its characteristics such as its large volume and nonvolatile feature, low power consumption, and good performance. However, a block in flash memories should be erased to write because of its hardware characteristic which is called as erase-before-write architecture. The erase operation is much slower than read or write operations. FTL is used to overcome this problem. We compared the performance of the existing FTL algorithms on Windows-based OS. We have developed a tool called FTL APAT in order to gather I/O patterns of the disk and analyze the performance of the FTL algorithms. It is the log buffer scheme with full associative sector translation(FAST) that the performance is best.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.8
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• pp.3610-3616
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• 2011

Electrical Railroads provide electric power, which can operate vehicles, via feeder wires. And the supplied current returns to the transformer substation through lines and ground net. The used load current depending on the operation of rail vehicles in the electric railway sections returns to the substation through a track which is a return circuit. The load current contains harmonics because of the power conversion equipment used in rolling stocks and such harmonic currents should not affect train control system. In this paper we present the test result in order to verify that the harmonics produced by the operation of rail vehicles in the newly built electric railway sections can affect interlocking systems. The test in question was performed in a linking section that trackside equipment under railway operating conditions and interlocking are linked in order to identify whether or not the interlocking fitted in a signal machine room can be affected by harmonics according to railway operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.397-401
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• 2005

In this paper, we have developed a frequency mixer which can be used as a microwave phase conjugator in the retrodirective array antenna. The retrodirective array, which can reflect the incident wave retrodirertively back to the source direction without any priori information, requires phase conjugators to achieve the phase change of 180 degrees for the incoming signal. frequency mixers can efficiently serve as phase conjugators. The circuit topology is of the 2-port structure to avoid the complexity of LO and Rf signal combination and matching circuits, using a pseudomorphic HEU device. The operating frequencies are 4.0 CHz, 2.01 CHz, and 1.99 CHz for LO, RF, and If signals, respectively. Conversion loss is measured to be -ldB and 1-dB compression point -l5 dBm at the LO power of -10 dBm.