• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.11
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• pp.27-32
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• 1999

Metal-ferroelectric-semiconductor devices by susing rapid thermal annealed $LiNbO_3/Si$(100) structures were fabricated and demonstrated nonvolatile memory operations. The estimated field-effect electron mobility and transconductance on a linear region of the fabricated FET were about $600cm^2/V{\cdot}s$ and 0.16mS/mm, respectively. The ID-VG characteristics of MFSFET's showed a hysteresis loop due to the ferroelectric nature of the $LiNbO_3 films. The drain current of the on state was more than 4 orders of magnitude larger than the off state current at the same read gate voltage of 0.5V, which means the memory operation of the MFSFET. A write voltage as low as ${\pm}3V$, which is applicable to low power integrated circuits, was used for polarization reversal. The ferroelectric capacitors showed no polarization degradation up to $10^{10}$ switching cycles with the application of symmetric bipolar voltage pulse (peak-to-peak 6V, 50% duty cycle) of 500kHz.

• Journal of the Korean Vacuum Society
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• v.12 no.2
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• pp.130-135
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• 2003

Polycrystalline silicon thin films have been used for low cost thin film device application. However, it was very difficult to fabricate high performance poly-Si at a temperature lower than $600^{\circ}C$ for glass substrate because the crystallization process technologies like conventional solid phase crystallization (SPC) require the number of high temperature (600-$1000^{\circ}C$) process. The objective of this paper is to grow poly-Si on flexible substrate using a rapid thermal crystallization (RTC) of amorphous silicon (a-Si) layer and make the high temperature process possible on molybdenum substrate. For the high temperature poly-Si growth, we deposited the a-Si film on the molybdenum sheet having a thickness of 150 $\mu\textrm{m}$ as flexible and low cost substrate. For crystallization, the heat treatment was performed in a RTA system. The experimental results show the grain size larger than 0.5 $\mu\textrm{m}$ and conductivity of $10^{-5}$ S/cm. The a-Si was crystallized at $1050^{\circ}C$ within 3min and improved crystal volume fraction of 92 % by RTA. We have successfully achieved a field effect mobility over 67 $\textrm{cm}^2$/Vs.

• Journal of Sensor Science and Technology
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• v.2 no.1
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• pp.95-99
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• 1993

a-Si : H TFTs for image sensor have been fabricated and their operational characteristics have been investigated. Hydrogenated amorphous silicon nitride(a-SiN : H) films were used for the gate insulator and $n^{+}$-a-Si : H films were depostied for the source and drain contact. The thicknesses of a-SiN : H and a-Si : H films were $2000{\AA}$, respectively and the thickness of $n^{+}$-a-Si : H film was $500{\AA}$. Also the channel length and channel width of a-Si : H TFTs were $50{\mu}m$ and $1000{\mu}m$, respectively. The ON/OFF current ratio, threshold voltage, and field effect mobility of fabricated a-Si : H TFTs were $10^{5}$, 6.3 V, and $0.15cm^{2}/V{\cdot}s$, respectively.

• Journal of the Korean Vacuum Society
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• v.16 no.5
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• pp.359-365
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• 2007

In this paper we present a bottom-gate type of zinc oxide (ZnO) and Gallium (Ga) doped zinc oxide (GZO) based thin film transistors (TFTs) through applying a radio frequency (RF) magnetron sputtering method at room temperature. The gate leakage current can be reduced up to several ph by applying $SiO_2$ thermally grown instead of using new gate oxide materials. The root mean square (RMS) values of the ZnO and GZO film surface were measured as 1.07 nm and 1.65 nm, respectively. Also, the transmittances of the ZnO and GZO film were more than 80% and 75%, respectively, and they were changed as their film thickness. The ZnO and GZO film had a wurtzite structure that was arranged well as a (002) orientation. The ZnO TFT had a threshold voltage of 2.5 V, a field effect mobility of $0.027\;cm^2/(V{\cdot}s)$, a on/off ratio of $10^4$, a gate voltage swing of 17 V/decade and it operated in a enhancement mode. In case of the GZO TFT, it operated in a depletion mode with a threshold voltage of -3.4 V, a field effect mobility of $0.023\;cm^2/(V{\cdot}s)$, a on/off ratio of $2{\times}10^4$ and a gate voltage swing of 3.3 V/decade. We successfully demonstrated that the TFTs with the enhancement and depletion mode type can be fabricated by using pure ZnO and 1wt% Ga-doped ZnO.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.8
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• pp.14-18
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• 2018

Generally. the Ohmic's law is an important factor to increase the conductivity in a micro device. So it is also known that the Ohmic contact in a semiconductor device is import. The PN junction as a structure of semiconductor involves the depletion layer, and this depletion layer induces the non linear electrical properties and also makes the Schottky contact as an intrinsic characteristics of semiconductor. To research the conduction effect of insulators in the semiconductor device, $SiO_2$ thin film and $V_2O_5/SiO_2$ thin film were researched by using the current-voltage system. In the nano electro-magnetic system, the $SiO_2$ thin film as a insulator had the non linear Schottky contact, and the as deposited $V_2O_5$ thin film had the linear Ohmic contact owing to the $SiO_2$ thin film with superior insulator's properties, which decreases the leakage current. In the positive voltage, the capacitance of $SiO_2$ thin film was very low, but that of $V_2O_5$ thin film increased with increasing the voltage. In the normal electric field system, it was confirmed that the conductivity of $V_2O_5$ thin film was increased by the effect of $SiO_2$ thin film. It was confirmed that the Schottky contact of semiconductors enhanced the performance of electrical properties to increased the conductivity.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.6
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• pp.648-654
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• 2003

Diamond MIS(Metal-Insulator-Semiconductor) diodes and MISFETs(Metal-Insulator-Semiconductor Field Effect Transistors) were fabricated by employing various fluorides as gate insulator, and their electrical properties were closely investigated by means of C-V measurements. The A1/BaF$_2$/diamond MIS structure exhibited outstanding electrical properties. The MIS diode showed a very low surface state density of ∼10$\^$10//$\textrm{cm}^2$ eV near the valence band edge, and the observed effective mobility(${\mu}$$\_$eff/) of the MISFET was 400 $\textrm{cm}^2$/Vs, which is the highest value obtained until now in the diamond FET. From the chemiphysical point of view, the above result might be explained by the reduction of adsorbed-oxygen on the diamond surface via strong chemical reaction by the constituent Ba atom in the insulator during the film deposition(Oxygen-Gettering Effect).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.390-397
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• 2001

A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer and recessed-channel depth which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current Is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side.

• Journal of Adhesion and Interface
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• v.20 no.4
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• pp.155-161
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• 2019

Understanding charge transport anisotropy at the interface of conjugated nanostructures basically gives insight into structure-property relationship in organic field-effect transistors (OFET). Here, the anisotropy of the field-effect mobility at the interface between 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) single crystal with cofacial molecular stacks in a-b basal plane and SiO gate dielectric was investigated. A solvent exchange method has been used in order for TIPS-pentacene single crystals to be grown on the surface of SiO₂ thin film, corresponding to the charge accumulation at the interface in OFET structure. In TIPS-pentacene OFET, the anisotropy ratio between the highest and lowest measured mobility is revealed to be 5.2. By analyzing the interaction of a conjugated unit in TIPS-pentacene with the nearest neighbor units, the mobility anisotropy can be rationalized by differences in HOMO-level coupling and hopping routes of charge carriers. The theoretical estimation of anisotropy based on HOMO-level coupling is also consistent with the experimental result.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.157-161
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• 2000

본 논문은 2린 대역의 마이크로 셀 환경에서 원편파 특성을 분석하기 위하여 편파의 특성을 이론적 해석과 실제 측정 데이터를 비교 검토하였다. 가시거리에서는 원편파가 기수회 반사파 수신을 억제하기 때문에 다중경로 페이딩에 대한 경감 효과가 있다는 것은 널리 알려져 있다. 본 연구팀은 "E"자형 건물의 회절 음영 지역에서도 원편파의 편파 특성이 잘 유지되는지를 측정 분석하였다. 이를 위해 정선회 원편파(C), 역선회 원편파(X), 수직편파(V), 수평편파(H) 안테나를 사용하여 각각의 송수신 편파간 조합에 대하여 거리에 따른 전계강도를 이동 측정하였다. 전파 모델은 "E"자형 건물의 회절지역 모델에서 2개의 경로를 선택하여 각각에 대한 전파의 편파 특성을 분석하였다.대한 전파의 편파 특성을 분석하였다.

• Proceedings of the KIEE Conference
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• 2002.07a
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• pp.475-477
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• 2002

본 논문에서는 765kV 송전선로의 일부구간에서 발생되고 있는 풍소음의 대책으로 개발된 저풍소음 도체를 소개하고 이 도체방식을 개발하기 위해 수행된 전기환경장해 및 풍소음 저감 영향에 대한 시험결과를 제시하고 있다. 저풍소음 도체는 우수한 풍소음 저감기능을 가지면서도 기존 전선에 비해 추가적인 전기환경 문제가 발생되지 않아야 하는데, 기존 전선과 달리 전선 주위에 돌기부가 있어서 전계 집중에 따른 환경장해 발생의 우려가 있다. 이러한 이유 때문에 전기환경 모의시험설비인 코로나 케이지를 이용한 코로나 발생 특성 시험을 수행하여 환경설계기준 만족 여부를 확인하였으며, 실규모 시험선로를 이용한 장기 실증시험을 실시하여 송전선로 주변에서 실제 발생 가능한 라디오 장해와 같은 전기환경 장해량에 대한 평가를 실시하여 풍소음 저감효과와 환경설계기준에 만족하는 결과를 얻을 수 있었다.