• Title/Summary/Keyword: 적층제작공정

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Design Optimization for High Efficiency Distributed Bragg Reflectors through Simulation Methodology (시뮬레이션을 이용한 고효율 분산 브래그 반사경 최적화 설계 및 특성)

  • Kim, Kwan-Do
    • Journal of IKEEE
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    • v.22 no.1
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    • pp.189-192
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    • 2018
  • This study focused on the development of simulation methodology and design optimization for the DBR(Distributed Bragg Reflectors) structures, which are commonly used in manufacturing optical films and the key components of LED chip and LCD inspection equipments. From the multi-layer simulation, the following results are obtained. First, the wavelength(nm) vs. reflectance(%) can be calculated in the DBR structures that $TiO_2$ and $SiO_2$ thin films are stacked alternately. As a results, it is suggested that highly efficient DBR structures can be designed and manufactured using simulation methodology.

Cu2ZnSnS4 박막 및 소자 특성에 대한 전구체에 Zn 또는 ZnS 타겟을 사용 했을 때의 효과

  • Im, Gwang-Su;Yu, Seong-Man;Lee, Jeong-Hun;Sin, Dong-Uk;Yu, Ji-Beom
    • Proceedings of the Korean Vacuum Society Conference
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    • 2016.02a
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    • pp.407.2-407.2
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    • 2016
  • Cu2ZnSnS4 (CZTS) 박막은 낮은 가격과 유리한 특성을 가지므로서 차세대 박막 태양전지에서 이상적인 흡수층 물질 중 하나로 여겨지고 있다. 우리는 CZTS 박막 태양전지를 합성하는 데 있어서 Zn와 ZnS를 전구체에 사용하여 이에 따른 특성 차이를 연구하였다. 열처리 한 박막은 Zn와 ZnS를 사용하였을 때 특성 차이를 조사하기 위하여 여러 분석을 진행하였다. CZTS 박막의 미세구조와 조성 분포, 전기적 특성을 살펴보았다. Zn를 사용한 CZTS 박막은 큰 입자크기와 더 적은 영역에서 Zn가 집중되어 있는 층을 가진다. CZTS와 Mo 경계인 이 영역에 ZnS 2차상이 존재함을 의미하며 Zn 타겟을 사용하였을 때 더 낮은 Zn 조성을 가지는 것을 확인하였고 이는 결과적으로 접합 특성의 향상을 가져온다. 제작 된 CZTS 태양 전지 소자에서 이러한 이유로 Zn를 사용하였을 때 5.06%로 ZnS를 사용하였을 때에 비하여 더 높은 효율을 얻을 수 있었다.

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A 2-Gbps Simultaneous Bidirectional Inductively-Coupled Link (동시 양방향 통신이 가능한 2-Gbps 인덕터 결합 링크)

  • Jeon, Minki;Yoo, Changsik
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.3
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    • pp.42-49
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    • 2013
  • A simultaneous bidirectional inductively-coupled link is presented. In the conventional inductively-coupled link, data can be bidirectionally transmitted through channel, however not simultaneously. We propose simultaneous bidirectional link for higher data rate with effective echo cancellation technique. Each chip performs TX-mode and RX-mode simultaneously. Instead chip stacking for test, similar test enviroment is realized in a single chip that is fabricated in a $0.13-{\mu}m$ standard CMOS technology.

Rapid Manufacturing of Large Object by Splitting Solid Model in VLM-ST (VLM-ST 공정에서 입체 절단을 이용한 대형 물체의 쾌속 제작)

  • 이상호;안동규;김효찬;양동열;채희창
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2003.06a
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    • pp.50-53
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    • 2003
  • Most companies use technologies such as stereolithography, selective laser sintering, and fused deposition modeling to make parts for such small consumer products as telephones, heads, and shoes. The largest part that the existing RP systems can make is only 600 mm in length. Because most RP systems build parts by depositing, solidifying, or sintering material point-by-point, making larger objects takes a long time. and in many cases, large objects won't fit the build size. A new effective thick-layered RP process. Transfer type Variable Lamination Manufacturing using expandable polystyrene foam (VLM-ST) has been developed with thick layers and sloped surfaces. In this paper, a scaledown model of F16 Fighter with the length of 800 mm is rapidly fabricated using the VLM-ST process. In order to build a CAD model of F16 larger than 600 mm in length, the approach in VLM-ST is to build larger parts in multiple sub-parts and then glue them together. The fabricated result shows that the VLM-ST process employing thick layers and sloped surfaces is adequate for creating the real-sized large objects in the diverse fields such as automobiles, electric home appliances, electronics. and etc.

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Heat Treatment Effects of Staggered Tunnel Barrier (Si3N4 / HfAlO) for Non-volatile Memory Application

  • Jo, Won-Ju;Lee, Se-Won
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.08a
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    • pp.196-197
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    • 2010
  • NAND형 charge trap flash (CTF) non-volatile memory (NVM) 소자가 30nm node 이하로 고집적화 되면서, 기존의 SONOS형 CTF NVM의 tunnel barrier로 쓰이는 SiO2는 direct tunneling과 stress induced leakage current (SILC)등의 효과로 인해 data retention의 감소 등 물리적인 한계에 이르렀다. 이에 따라 개선된 retention과 빠른 쓰기/지우기 속도를 만족시키기 위해서 tunnel barrier engineering (TBE)가 제안되었다. TBE NVM은 tunnel layer의 전위장벽을 엔지니어드함으로써 낮은 전압에서 전계의 민감도를 향상 시켜 동일한 두께의 단일 SiO2 터널베리어 보다 빠른 쓰기/지우기 속도를 확보할 수 있다. 또한 최근에 각광받는 high-k 물질을 TBE NVM에 적용시키는 연구가 활발히 진행 중이다. 본 연구에서는 Si3N4와 HfAlO (HfO2 : Al2O3 = 1:3)을 적층시켜 staggered의 새로운 구조의 tunnel barrier Capacitor를 제작하여 전기적 특성을 후속 열처리 온도와 방법에 따라 평가하였다. 실험은 n-type Si (100) wafer를 RCA 클리닝 실시한 후 Low pressure chemical vapor deposition (LPCVD)를 이용하여 Si3N4 3 nm 증착 후, Atomic layer deposition (ALD)를 이용하여 HfAlO를 3 nm 증착하였다. 게이트 전극은 e-beam evaporation을 이용하여 Al를 150 nm 증착하였다. 후속 열처리는 수소가 2% 함유된 질소 분위기에서 $300^{\circ}C$$450^{\circ}C$에서 Forming gas annealing (FGA) 실시하였고 질소 분위기에서 $600^{\circ}C{\sim}1000^{\circ}C$까지 Rapid thermal annealing (RTA)을 각각 실시하였다. 전기적 특성 분석은 후속 열처리 공정의 온도와 열처리 방법에 따라 Current-voltage와 Capacitance-voltage 특성을 조사하였다.

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Design of a Low Noise Ultraminiature VCO using the InGap/GaAs HBT Technology (InGaP/GaAs HBT 기술을 이용한 저잡음 극소형 VCO 설계)

  • 전성원;이상설
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.15 no.1
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    • pp.68-72
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    • 2004
  • The integrated voltage-controlled-oscillator(VOC) operating at 1.75 ㎓ is designed using the InGaP/GaAs HBT process. The proposed noise removal circuit and FR-4 substrate structure in this letter show the better characteristic of the phase noise and reduce the size of the VCO. The frequency tuning range of the VCO is about 200 ㎒ and the phase noise at 120 ㎑ offset is -119.3 ㏈c/㎐. The power consumption of the VCO core is 11.2 ㎽ at 2.8 V supply voltage and the output power is -2 ㏈m. The calculated figure of merit(FOM) is 191.7, which shows the best performance compared with the previous FET or HBT VCO.

A Study on Fabrication of Internally Colored Shape in Stereolithography Parts using Molten Ink Deposition Process (용융잉크 적층공정을 이용한 내부채색형상을 포함한 광조형물 제작에 관한 연구)

  • Park, Jong-Cheol;Park, Suk-Hee;Kang, Sang-Il;Yang, Dong-Yol
    • Journal of the Korean Society for Precision Engineering
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    • v.27 no.6
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    • pp.98-104
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    • 2010
  • Rapid Prototypes with internally colored objects are convenient by visualizing. A rapid prototyping method has been developed to fabricate mono-colored or multi-colored objects. In this work, a new process was proposed that can fabricate internally visible colored 3D objects in stereolithography parts. The process consists of projection stereolithography process using transparent photocurable resin for outer shapes and molten ink deposition process using molten solid ink for internal shapes. In molten ink deposition process, molten solid ink could be deposited uniformly in a designed pattern. To make molten solid ink uniform over a designed region, parametric study through a patterning solid ink was performed. By laminating resin and solid ink in sequence, the process can make colored 3D objects in StereoLithography(SL) parts. The practicality and effectiveness of the proposed process were verified through fabrication of colored basic 3D objects in SL parts.

Image Processing Method using Color Lines on Overlay Robot for Glass Fiber Pipe/Duct Joint (유리섬유 배관/덕트 조인트 접합 로봇의 주행 및 공정을 위한 색상 실선의 영상처리)

  • Baek, J.H.;Jeong, M.S.;Jang, M.W.;Hong, S.H.;Seo, K.H.;Suh, J.H.;Lee, G.S.;Lee, J.Y.
    • Proceedings of the Korea Information Processing Society Conference
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    • 2019.10a
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    • pp.1090-1093
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    • 2019
  • 유리섬유강화복합재료로 제작된 배관/덕트 조인트의 오버레이 자동접합을 할 수 있는 로봇이 개발되고 있으며 로봇의 구성 중 하나인 자동적층장치의 작업 시작 위치와 제자리 회전 오차를 극복할 수 있는 기준선에 대한 실시간 영상처리가 필요하다. 기존의 선 검출 알고리즘들은 연산량이 많아 실시간 처리가 어렵거나 전체 영상에서 잡음에 취약한 단점이 있다. 본 논문은 이러한 FRP 배관 및 덕트 내 색상 실선 인식 알고리즘의 효율적인 실시간 영상처리 방법에 관하여 소개하고 배관 내 라인 제어를 위한 선의 실제 거리를 계산하고 출력하는 방법을 나타내었다.

A Study on Optimization of Inkjet-based IDE Pattern Process for Impedance Sensor (임피던스 센서 제작을 위한 잉크젯 기반 패턴 IDE 적층공정 최적화 연구)

  • Jeong, Hyeon-Yun;Ko, Jeong-Beom
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.21 no.4
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    • pp.107-113
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    • 2022
  • At present, it is possible to manufacture electrodes down to several micrometers (~ ㎛) using inkjet printing technology owing to the development of precision ejection heads. Inkjet printing technology is also used in the manufacturing of bio-sensors, electronic sensors, and flexible displays. To reduce the difference between the electrode design/simulation performance and actual printing pattern performance, it is necessary to analyze and optimize the processable area of the ink material, which is a fluid. In this study, process optimization was conducted to manufacture an IDE pattern and fabricate an impedance sensor. A total of 25 IDE patterns were produced, with five for each lamination process. Electrode line width and height changes were measured by stacking the designed IDE pattern with a nanoparticle-based conductive ink multilayer. Furthermore, the optimal process area for securing a performance close to the design result was analyzed through impedance and capacitance. It was observed that the increase in the height of stack layer 4 was the lowest at 4.106%, and the increase in capacitance was measured to be the highest at 44.08%. The proposed stacking process pattern, which is optimized in terms of uniformity, reproducibility, and performance, can be efficiently applied to bio-applications such as biomaterial sensing with an impedance sensor.

A Study on Simplifying Flow Analysis of VaRI Process (VaRI 공정 유동해석 간소화 방법에 대한 연구)

  • Kim, Yeongmin;Lee, Jungwan;Kim, Jungsoo;Ahn, Sehoon;Oh, Youngseok;Yi, Jin Woo;Kim, Wiedae;Um, Moon-kwang
    • Composites Research
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    • v.34 no.4
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    • pp.233-240
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    • 2021
  • VaRI(Vacuum assisted Resin Infusion) process, which is cost effective and suitable for manufacturing large-sized composites, is an OoA(Out-of Autoclave) process. For rapid resin infusion in the VaRI process, a DM(distribution media) is placed on top of the fabric. The resin is rapidly supplied in plane direction of the fiber along the DM, and then the supplied resin is impregnated in the out-of-plane direction of fiber. It is difficult to predict the flow of resin because the flow of in-plane direction and the out-of-plane direction occur together, and a 3D numerical analysis program is used to simulate the resin infusion process. However, in order to analyze in 3D, many elements are required in the out-of-plane direction of fabric. And the product size is larger, the longer the analysis time needs. Therefore, in this study, a method was suggested to reduce the time required for flow analysis by simplifying the 3D flow analysis to 2D flow analysis. The usefulness was verified by comparing the 3D flow analysis with the simplified 2D flow analysis at the same conditions. The filling time error was about 7% and the reduction of flow analysis time was about 95%. In addition, by utilizing the constant difference in the flow front between the top, middle, and bottom of the fabric of the 3D analysis, the flow front of the top, middle, and bottom of the fabric can be also predicted in the 2D flow analysis.