• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.192-197
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• 2017

In this paper, image filter optimization method based on common sub-expression elimination is proposed for low-power image feature extraction hardware design. Low power and high performance object recognition hardware is essential for industrial robot which is used for factory automation. However, low area Gaussian gradient filter hardware design is required for object recognition hardware. For the hardware complexity reduction, we adopt the symmetric characteristic of the filter coefficients using the transposed form FIR filter hardware architecture. The proposed hardware architecture can be implemented without degradation of the edge detection data quality since the proposed hardware is implemented with original Gaussian gradient filtering algorithm. The expremental result shows the 50% of multiplier savings compared with previous work.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.45 no.5
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• pp.401-408
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• 2017

This paper describes development and validation processes of a low-cost hardware based flight control computer designed for multi-rotor UAVs. The developed flight control computer controls multi-rotors stable and can handle complex flight missions using an integrated high-performance Linux computer. A complementary filter generates a navigation solution with 500 Hz, and a proposed observer significantly reduces measurement noise. A control algorithm utilizes a feed-forward term computed by a three-dimensional curve fitting method, and it increases tracking performance. The developed flight control system has been fully tested through several test flights, and it can apply to real flight environments.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.143-146
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• 2001

본 논문에서는 다 채널 페이저 연산 장치를 전용하드웨어로 구현하기 위한 설계 구조에 대하여 제시하였으며, 이를 연산량이 많은 곱셈기를 시분할에 의해 공유하는 구조를 제시하였다. 또한 페이저 측정을 위한 Sliding-DFT 알고리즘을 순환 구현할 경우의 근사구현 오차에 관한 정량적인 연구를 수행하였다. 이러한 오차 영향의 해석을 기반으로 하여 곱셈기 공유 구조를 적용한 페이저 연산 장치를 설계하고, 설계한 하드웨어의 내부동작을 보여주는 시뮬레이션을 통해 설계의 정확성을 확인하였다

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.940-948
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• 2008

This paper presents a low-power, low-complexity design and implementation results of a high speed multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor is composed of the physical layer convergence procedure (PLCP) processor and physical medium dependent (PMD) processor, which have been optimized to have low-power and reduced-complexity architecture. It was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. As a result, the proposed TX-PLCP processor reduced the power consumption by as much as 81% over the bit-level operation architecture. Also, the proposed MIMO symbol detector reduced the hardware complexity by 18% over the conventional SQRD-based architecture with division circuits and square root operations.

• Journal of Korean Electronics
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• v.29 no.12
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• pp.8-16
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• 2009

금년 글로벌 시장 경기를 살펴보면, 미국발 금융위기로 세계시장이 동시에 불황에 직면하였다. 금년도 IT지출은 작년보다 5.2% 감소할 것으로 추정된다. 가트너 자료에 의하면, 컴퓨팅하드웨어부문에서 마이너스 16.5%로 가장 큰 타격을 입었고, 넷북 등 저가 제품의 수요 비중이 증가하며 IT하드웨어 업계의 수익을 압박한 것이다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.141-146
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• 2017

In this paper, a gradient magnitude hardware architecture based on hardware folding design method is proposed for low power image feature extraction. For the hardware complexity reduction, the projection vector chracteristic of gradient magnitude is applied. The proposed hardware architecture can be implemented with the small degradation of the gradient magnitude data quality. The FPGA implementation result shows the 41% of logic elements and 62% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v16.0 environment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.22-34
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• 2010

Existing image scalers generally adopt simple interpolation methods such as bilinear method to take cost-benefit, or highly complex architectures to achieve high quality resulting images. However, demands for a low power, low cost, and high performance image scaler become more important because of emerging high quality mobile contents. In this paper we propose the novel low power hardware architecture for a high quality raster scan image scaler. The proposed scaler architecture enhances the existing cubic interpolation look-up table architecture by reducing and optimizing memory access and hardware components. The input data buffer of existing image scaler is replaced with line memories to reduce the number of memory access that is critical to power consumption. The cubic interpolation formula used in existing look-up table architecture is also rearranged to reduce the number of the multipliers and look-up table size. Finally we analyze the optimized parameter sets of look-up table, which is a trade-off between quality of result image and hardware size.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.414-418
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• 2016

In this paper, a hardware architecture of low area gradient magnitude calculator is proposed. For the hardware complexity reduction, the characteristic of orthogonal projection vector and hardware resource sharing technique are applied. The proposed hardware architecture can be implemented without degradation of the gradient magnitude data quality since the proposed hardware is implemented with original algorithm. The FPGA implementation result shows the 15% of logic elements and 38% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v15.0 environment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10a
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• pp.281-286
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• 2006

배터리로 동작하는 휴대용 기기와 같은 임베디드 시스템은 복잡한 애플리케이션을 보다 오랜 시간 동안 동작할 수 있도록 하기 위해 하드웨어와 소프트웨어 측면 모두에서 저전력 기법의 구성이 필요하다. 한정된 하드웨어 시스템의 자원을 효율적으로 관리하고 보다 적은 전력소모를 위해서는 저전력 기법이 탑재된 저전력 실시간 운영체제가 필요하다. 본 논문에서는 IBM 과 MontaVista Software 에서 제안한 DPM(Dynamic Power Management) 기법을 적용한 저전력 실시간 운영체제를 설계 및 구현하였다.