• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.25-37
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• 1996

To process computer graphics in real time, the high-speed operations(multiplier and adder) are needed to increase the speed of graphic process. RNS(Residue Number System) is integer number system that has the parallel and high-speed operation. Also, it is able to design both high-speed multiplier and adder, since a cyclic group has an isomorphic relation between multiplication and addition in RNS. So in this paper, DRNS(Double Residue Number System) is proposed, it is used for the multiplier and the adder, which are designed using a circulative code for the high-speed graphic processor in RNS. The designed multiplier would operate with the speed of 87Mzz two TTL using 74s09 and 74s32.

• The Korean Journal of Financial Management
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• v.24 no.1
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• pp.59-83
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• 2007

In this paper, we test empirically free cash flows hypothesis about stock repurchase. The main results of this study can be summarized as follows. First, repurchasing firms do not experience a growth in profitability relative to their peer firms. Second, repurchasing firms experience a contraction in their investment opportunity, and so capital expenditures and cash reserves decline after the repurchase. Third, repurchasing firms experience a decline in systematic risk and investments and in their cost of capital. Fourth, the reduction in profitability and cost of capital are sources of the positive market reaction to the repurchase announcement. And the market reaction to stock repurchase announcements is stronger among those firms that are more likely to overinvest. Conclusively, these results support free cash flows hypothesis. When firms experience a decline in profitability, capital expenditures and cash reserves, systematic risk and cost of capital, they decide to repurchase stocks to reduce free cash flows.

• Journal of the Korea Society of Computer and Information
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• v.12 no.3
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• pp.37-50
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• 2007

In this paper, we designed and implementation of the high speed neuron processor for real time object recognition in the making automatic system. and we designed of the PE(Processing Element) used residue number system without carry propagation for the high speed operation. Consisting of MAC(Multiplication and Accumulation) operator using residue number system and sigmoid function operator unit using MAC(Mixed Radix conversion) is designed. The designed circuits are descript by C language and VHDL(Very High Speed Integrated Circuit Hardware Description Language) and synthesized by compass tools and finally, the designed processor is fabricated in $0.8{\mu}m$ CMOS process. we designed of MAC operation unit and sigmoid proceeding unit are proved that it could run time 0.6nsec on the simulation and improved to the speed of the three times and decreased to hardware size about 50%, each order. The designed neuron processor can be implemented of the object recognition in making automatic system with desired real time processing.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.662-665
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• 1988

This paper proposes the Minimum-Distance Classification(MDC) processor using the Residue Number System(RNS). The proposed MDC Processor in this paper is efficient for real-time pattern clustering application and illustrate satisfiable error rate in application experiments of image segmentation but error rate increase as cluster number do.

• Journal of the Korean Geographical Society
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• v.32 no.2
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• pp.229-244
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• 1997

This study investigates the spatial policy of small towns in China. Small towns in China are important in terms of settlement system, rural urbanization and new adaptation to changing situation. It was necessary that they shoud take charge of the tool for solving the problem in rural reform periods. Rural urbanization, which had aimed at transferring the surplus labor smoothlv, was connected with the growth of rural industrialization (a township enterprise). However, the location of township enterprises was so dispersed that the transfer of surplus labors was not satisfactory. Hence, the concentration of the rural industry in small towns has been taken up as an inevitable alternative. Namely, it can be said that changes and adaptation of reform process, such as industrial restructuring and migration, should be integrated and concentrated in small towns.

• The Journal of Information Technology
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• v.2 no.2
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• pp.145-161
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• 1999

This paper proposes a high speed back propagation neural networks which uses the residue number system. making the high speed operation possible without carry propagation Consisting of MAC(Multiplication and Accumulation) operator unit using Residue number system and sigmoid function operator unit using Mixed Residue Conversion is designed, The Designed circuits are descripted by VHDL and synthesized by Compass tools. Result of simulations shows that critical path delay time is about 19nsec and the size can be reduced to 40% compared to the neural networks implemented by the real number operation unit. The proposed design circuits can be implemented in parallel distributed processing system with desired real time processing.

• 전자공학회논문지 IE
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• v.44 no.3
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• pp.12-22
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• 2007

In this paper, we designed of the high speed digital neuron processor in order to digital neural networks. we designed of the MAC(Multiplier and Accumulator) operation unit used residue number system without carry propagation for the high speed operation. and we implemented sigmoid active function which make it difficult to design neuron processor. The Designed circuits are descripted by VHDL and synthesized by Compass tools. we designed of MAC operation unit and sigmoid processing unit are proved that it could run time 19.6 nsec on the simulation and decreased to hardware size about 50%, each order. Designed digital neuron processor can be implementation in parallel distributed processing system with desired real time processing, In this paper.

• Proceedings of the Korean Nuclear Society Conference
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• 1997.05a
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• pp.51-56
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• 1997

기존 가압형 경수로에서 전체 반응도가의 상당부분을 제어하고 있는 붕산수를 사용하지 않고 노심 잉여반 응도를 보상하기 위해 1300MWe급 차세대원자로(KNGR)를 대상으로 무붕산노심 반응도 제어기법 연구를 수행하였다. 다양한 종류의 가연성독봉에 대한 무봉산노심 적용가능성을 분석하고 새로운 개념의 Enriched WABA를 도입하였다. Enriched WABA는 전 주기동안 무붕산노심에 적합한 반응도 제어능력을 나타내었고, 18개월 주기의 무붕산 차세대원자로 개념설계에 효과적으로 사용되었다. 핵연료집합체 군정수 생산 및 노심해석에는 Westinghouse사의 APA(ALPHA/PHOENIX-P/ANC) 전산코드체계를 사용하였고, 본 연구로부터 한단계 높은 안전성을 제공하는 무붕산운전은 충분한 가능성이 있다고 판단된다.

• Journal of the Korea Society of Computer and Information
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• v.4 no.2
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• pp.27-38
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• 1999

This paper proposes a high speed digital neuron processor which uses the residue number system, making the high speed operation possible without carry propagation,. Consisting of the MAC(Multiplier and with Accumulator) operation unit, quotient operation unit and sigmoid function operation unit, the neuron processor is designed through 0.8$\mu$m CMOS fabrication. The result shows that the new implemented neuron processor can run at the speed of 19.2 nSec and the size can be reduced to 1/2 compared to the neuron processor implemented by the real number operation unit.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.87-93
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• 1989

Squared-error Pattern Clustering algorithm used in unsupervised pattern recognition and image processing application demands substantial processing time for operation of feature vector matrix. So, this paper propose the fast squared-error Pattern Clustering Processor using the Residue Number System which have been the nature of parallel processing and pipeline. The proposed Squared-error Pattern Clustering Processor illustrate satisfiable error rate for Cluster number which can be divide meaningful region and about 200 times faster than 80287 coprocessor from experiments result of image segmentation. In this result, it is useful to real-time processing application for large data.