• The Journal of the Acoustical Society of Korea
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• v.30 no.3
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• pp.149-157
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• 2011

In this paper, we propose a new cardiac disorder classification method using an support vector machine (SVM) to combine hidden Markov model (HMM) and murmur existence information. Using cepstral features and the HMM Viterbi algorithm, we segment input heart sound signals into HMM states for each cardiac disorder model and compute log-likelihood (score) for every state in the model. To exploit the temporal position characteristics of murmur signals, we divide the input signals into two subbands and compute murmur probability of every subband of each frame, and obtain the murmur score for each state by using the state segmentation information obtained from the Viterbi algorithm. With an input vector containing the HMM state scores and the murmur scores for all cardiac disorder models, SVM finally decides the cardiac disorder category. In cardiac disorder classification experimental results, the proposed method shows the relatively improvement rate of 20.4 % compared to the HMM-based classifier with the conventional cepstral features.

• Korean Journal of Optics and Photonics
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• v.14 no.4
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• pp.473-479
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• 2003

The purpose of this study is to recover the CIE XYZ tristimulus values of original colors from scanner output signals, and to reproduce true colors on the monitor. The process of this study is composed of three steps; scanner characterization, chromatic adaptation transformation, and color space transformation between and sRGB. Especially, in the process of recovery, scanner stimuli were obtained accurately by dividing the non-linear photometric response curve into two parts. As the result of test to EPSON Expression 1680 scanner, the average color difference between true and recovered XYZ for 228 target colors, 22 test neutrals, and 36 test colors were 1.49, 0.97, and 1.42 $\Delta$ $E_{UV}$ *, respectively. With the transformation from illuminant D50 to illuminant D65, the input signals to sRGB monitor were predicted. Finally, it could be found that displayed colors with predicted input signals were very consistent with true colors. with true colors.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.6
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• pp.29-34
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• 2007

It is important to analyse the frequency spectrum for the measurement of modulated signal, distortion, and noise. The frequency spectrum analysis is performed by the execution of Radix-2 DIT DFT i.e. FFT algorithm. The discrete input signal converted by A/D converter from the input signal in time domain is mathematically transformed to the frequency spectrum by FFT algorithm. In this study, we design the digital spectrum analyser by the hardware based on the TMS320F2812 DSP and AD9244 converter, and by the software based on the C28x S/W modules. We can timely analyse the frequency spectrum in mobile communication system by the digital frequency analyser based on the high performance DSP and S/W modules. This real-time analysing capability is the important performance in the internet-based mobile communication server system.

• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.938-946
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• 1996

Hierarchical subband codec has been widely promoted in the field of data compression/decompression because of their simplicity and modular nature. Over the past years, the study has received great attention to the perfect reconstruction (PR)system which perfectly recovers the original input signal at the reconstructed output. However, in the actual subband codec system, the signals that passed through the analysis filter bank are quantized before transmission to the receiver side and reconstructed by the synthesis filter bank. Thus the PR system is impossible and the quantization effects must be carefully considered in the system design such that the system recovers the reconstructed output as possible to the the original input signal with minimum quantization error.In this paper, we propose an optimum hierarchical subband codec structure in the presence of quantizer. The optimality criteria of the code is given to the deign of the hierarchical analysis/synthesis subband filter bank and the quantizer that minimize then output mean square error due to the quantizer in the codec. Specific opti-mum design esamples are shown with level-1, level-2 hierarchical structure. The optimal designs are verified by computer simulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.10 s.101
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• pp.1010-1019
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• 2005

In this paper, we used neural network technique to model memory effects of RF power amplifier which is fed by two-tone input signals. The memory effects in power amplifier were identified by observing the unsymmetrical distribution of IMD(Inter-Modulation Distortion) measurements with the change of tone spacings and power levels. Different asymmetries of IMD were also found at different center frequencies. We applied TDNN technique to model LDMOS power amplifier based on two tone IMD data, and the accuracy was very high compared to other modeling methods such as the(memoryless) adaptive modeling method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.638-646
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• 2005

In recent wireless communications, direct conversion transceiver or If sampling SDR-based receivers have being designed as an alternative to conventional transceiver topologies. In direct conversion receiver a.chitectu.e, the 1.equency/phase offset between the RF input signal and the local oscillator signal is a major impairment factor even though the conventional AFC/APC compensates the service deterioration due to the offset. To rover the limited tracking range of the conventional method and effectively aid compensation scheme in terms of I/Q channel imbalances, the frequency/phase offset compensation in RF-front end signal stage is proposed in this paper. In RF-front end, the varying phase offset besides the fixed large frequency/phase offset are corrected by using early-late phase compensator. A more simple frequency and phase tacking function in digital signal processing stage of direct conversion receiver is effectively available by an ingenious frequency/phase offset tracking method in RF front-end stage.

• The Journal of the Korea Contents Association
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• v.7 no.6
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• pp.44-51
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• 2007

For real-time recognizing of model objects in remote position a new Neural Networks algorithm is proposed. The proposed neural networks technique is the real time computation methods through the inter-node diffusion. In the networks, a node corresponds to a state in the quantized input space. Each node is composed of a processing unit and fixed weights from its neighbor nodes as well as its input terminal. The most reliable algorithm derived for real time recognition of objects, is a dynamic programming based algorithm based on sequence matching techniques that would process the data as it arrives and could therefore provide continuously updated neighbor information estimates. Through several simulation experiments, real time reconstruction of the nonlinear image information is processed. 1-D LIPN hardware has been composed and various experiments with static and dynamic signals have been implemented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2064-2071
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• 1998

A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.12
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• pp.1274-1285
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• 1991

This paper presents a statistical convergence analysis of the normalized least mean square(NLMS)algorithm that employs a single-pole lowpass filter, In this algorithm the lowpass filter is used to adjust its output towards the estimated value of the input signal power recursively. The estimated input signal power so obtained at each time is then used to normalize the convergence parameter. Under the assumption that the primary and reference inputs to the adaptive filter are zero mean wide sense stationary, and Gaussian random processes, and further making use of the independence assumption. we derive expressions that characterize the mean and maen squared behavior of the filter coefficients as well as the mean squared estimation error. Conditions for the mean and mean squared convergence are explored. Comparisons are also made between the performance of the NLMS algorithm and that of the popular least mean square(LMS) algorithm Finally, experimental results that show very good agreement between the analytical and emprincal results are presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.826-832
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• 2004

A CMOS 8 bit folding and interpolating ADC for an embedded system inside VLSI is presented in this paper. This folding ADC uses the 2 stage architecture for improving of nonlinearity. repeating the folding and interpolating twice. At a proposed structure, a transistor differential pair operates on the second folder. A ADC with 2 stage architecture reduces the number of comparators and resisters. So it is possible to provide small chip size, low power consumption and high operating speed. The design technology is based on fully standard 0.25m double-Poly 2 metal n-well CMOS Process. The simulated Power consumption is 45mW with an applied voltage of 2.5V and sampling frequency of 250MHz. The INL and DNL are within <ㅆㄸㅌ>$\pm$0.2LSB, respectively. The SNDR is approximately 45dB for input frequency of 10MHz.