• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1996.11a
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• pp.205-218
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• 1996

World Wide Web(WWW) has a lot of useful charaters. Easiness of use, multi-media data supporting and interactive communication capability are typical reasons why people want to use WWW. But because WWW is based on Internet, it has some security problems which originate in plain format data transmission on physical transmission line. The unique solution fer this problems is data encryption. Since theoritically proved encryption algorithms ensure data confidentiality, a unauthorized user can not know what is transmitted on network. In this paper, we propose a cryptography system which uses public key system. In detail, our public key based web security mechanism is using PGP module. PGP is a e-mail security system implemented by Phil Zimmermann. The basic idea of our propose is data encryption and integrity checking for all data which is transmitted on Web. To implement these facilities, we. use netscape browser extension technology, plug-in. Through these technology, security mechanisms are added on netscape browser.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.812-820
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• 2006

Ethernet has been given a greater attention recently due to tendency of unifying most of transmission technique(not only LAN, but MAN and WAN) to ethernet. Performance evaluation was performed using C language for 10Gbps ethernet Data Link to design the optimum hardware, then internal FIFO size was evaluated. In this paper, MAC core for 10Gbps ethernet which contains high layer interface, transmit engine, flow control block, receive engine, reconciliation sublayer, configuration block, statistics block, and XGMII interface block was designed using VHDL language and Xilinx 6.2i tool and verified using Model_SIM 5.7G simulator. According to the specification of 10Gbps ethernet, MAC core with 64-bit data path should support 156.25MHz in order to support 10Gbps. The designed MAC core that process 64-bit data, operates at 168.549MHz and hence supports the maximum 10.78Gbps data processing. The designed MAC core is applicable to an area that needs a high-speed data processing of 10Gbps or more.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.93-99
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• 2017

In this research the TOF (time of flight) of ultrasonic signal is measured using Xilinx's Zynq SoC (system on chip). The TOF is calculated from the difference between periods during which RF (radio frequency) and ultrasonic signals come across a distance, and then travelling distance is obtained by multiplying the TOF by the ultrasonic speed in the air. For this purpose, a ultrasonic pulse is generated from a Zynq's internal ADC, a FIR (finite impulse response) filter, and a Kalman filter. And a RF reference pulse is generated from a RF interface. Based on baremetal multiprocessing, the Kalman filter and the RF interface are c-programmed on Zynq's dual processor cores, with other components fabricated on Zynq's FPGA. With this HW/SW co-design, both lower resource utilization and much smaller designing period were obtained than the HW design. As a design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.3
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• pp.326-331
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• 2010

This paper presents the design and implementation of a data acquisition system with a large number of multi-channels for manufacturing machine. The system having a throughput of 800-ch analog signals has been designed with Quartus II tool and Cyclone II FPGA. The proposed system is suitable for the large scale data handling in order to distinguish whether the operation is correct or not. The designed system is composed of a control unit, voltage divider and USB interface. To reduce the data throughput, we utilized an algorithm which can extract the same data from the achieved data. The test results of the system adapted to a manufacturing machine, show a relevant data acquisition operation of 800 channels in short time.

• Journal of Korea Multimedia Society
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• v.20 no.8
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• pp.1216-1223
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• 2017

Because of the open data in public domains, it is easy to collect the public data. However, people find difficulty in visualizing the data in material that they actually want. Especially, A map is a difficult material to do the visualization work, without using the specific tools and learning. Therefore, in this paper, we proposed an interface tool for map data visualization that user can easily visualize various national statistics data on the map. We designed the interface by classifying the properties of the map systematically, focusing on the completion and convenience for making the map. After that, we developed a web-based application using D3.js. After user evaluation, we found that our application can visualize the map more quickly and completely than any other web interfaces for map data visualization. Users also found a higher satisfaction in operating convenience.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04c
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• pp.579-581
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• 2003

본 논문은 웹사이트를 구성하는 웹컨텐츠의 합목적성 및 사용성 평가를 위하여 웹사이트 사용자들의 흔적인 웹로그 분석 데이터를 적용하여 정량적인 평가를 한 결과 에 대하여 보고 하고자 한다. 웹로그파일은 사용자가 웹사이트를 이용하면 이에 대한 기록이 로그라는 형태로 흔적이 남는다. 로그분석이란 이 데이터를 기반으로 위에서 말한 다양한 정보를 추출해 내는 것이라 할 수 있다. 로그분석은 사용자에 따라 단지 로그 정보를 분석하는 것에 한정시키기도, 로그 정보를 기반으로 한 보다 다양한 정보를 분석하는 확장된 개념으로 확대시키기도 한다. 본 논문은 웹트랜즈［로그분석 툴］를 사용하여 웹사이트내의 웹컨텐츠 분석에 웹 로그 분석 결과가 같는 정량적인 개념을 활용하여 정상적인 분석으로 일관되었던 웹사이트 분석에 새로운 결과를 도출하였다. 또한 마케팅을 수행하는 데 있어서 고객의 요구에 천저히 대응하기 위해서 고객을 철저히 파악하여야 한다. 로그파일 분석을 통해서 주요 고객층, 고객의 구매 패턴, 주 구매시간, 구매탐색 경로등의 데이터를 추출할 수 있다. 로그파일 분석 데이터를 기반으로 인터페이스 설계나 상품의 레이아웃등의 설계, 고객 서비스 강화등의 다양한 대 고객 마케팅을 펼칠 수 있다. 본 논문은 단순 수치해석의 개념이었던 로그 분석에 웹컨텐츠분석 기법을 접목하여 웹사이트내에서 사용되고 있는 컨텐츠의 사용성에 대안 연구 결과에 대해서 발표하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1442-1450
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• 1999

In this paper, we present an efficient hardware architecture for the frame memory of the MPEG-2 video encoder. Both the total size of internal buffers and the number of logic gates are reduced by the proposed memory map which can provide an effective interface between MPEG-2 video encoder and the external DRAM. Furthermore, the proposed scheme can reduce the DRAM access time. To realize the frame memory hardware,$0.5\mu\textrm{m}$, VTI, vemn5a3 standard cell library is used. VHDL simulator and logic synthesis tool are used for hardware design and RTL (register transfer level) function verification. The frame memory hardware emulator of the proposed architecture is designed for gate-level function verification. It is expected that the proposed frame memory hardware using VHDL can achieve suitable performance for MPEG-2 MP@ML.

• Annual Conference of KIPS
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• 2002.11c
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• pp.1681-1684
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• 2002

최근 XML 이라는 웹 문서 표준이 대두되면서 여러 응용 분야에서 이를 활용하려는 노력이 진행 중이다. 특히 웹 상에서 XML은 기준의 데이터베이스를 대체하여 데이터를 관리하고 조직화하며 또한 자원의 게시를 위해 사용되고 있다. 따라서 데이터베이스에 있는 데이터들을 XML문서로 변환하는 것은 필수불가분의 관계이며 좀더 쉽게 이러한 작업들을 할 수 있는 프로그램이 개발 또는 연구 중이다. 그러나 현재 개발된 XML 문서 변환기는 속성과 요소이름이 데이터베니스의 필드 이름으로 밖에 변환되지 않거나, 보통 테이블 이름이 요소로 각 필드이름이 요소 안의 속성으로 밖에 변환할 수 없다. 또한 MSSQL, MySQL, ACCESS와 같은 관계형 데이터베이스 툴 마다 호환이 되지 않으며 변환기 사용 시 인터페이스가 복잡하여 쉽게 이용할 수 없는 것이 현실이다. 본 논문은 이러한 문제점들을 해결하기 위해 효율적으로 관계형 데이터베이스 시스템에서 XML문서로 자동 변환시켜주는 웹 기반의 변환시스템을 구축하였다. 본 논문에서 제시한 변환 시스템은 데이터베이스 시스템 내의 테이블에 데이터를 입력할 경우 사용자가 원하는 형태의 XML문서로 변환이 가능하기 때문에 XML문서를 작성시 효과적으로 이용될 수 있다.

• Journal of the Korean BIBLIA Society for library and Information Science
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• v.21 no.2
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• pp.145-157
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• 2010

University library users prefer the internet to OPAC, when they search for information. It is necessary to develop interface of OPAC that is nearly as convenient as the internet. This study provides users with University Library Toolbar which is one of the ways to implement Web 2.0, and proved that OPAC is also a convenient and useful searching tool by offering the toolbar. In addition, the causes of the preferences of the internet sites surveyed for this study and the point shown in the comparison between the internet and OPAC are going to be essential materials to implement more convenient OPAC and Library 2.0.