• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.6A
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• pp.555-567
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• 2010

Unlike single-hop systems, multi-hop systems that use relay nodes assign a part of the overall resources to relay communications. If efficient resource allocation schemes are not adopted, this leads to a loss of resources. Moreover, because we may not be able to guarantee high-link performance due to the adjacent-cell interference in relay-based cellular systems, resource efficiency can be severely decreased. In this paper, we propose efficient resource allocation schemes for downlink relay-based networks in 3GPP (3rd Generation Partnership Project) LTE (Long Term Evolution)-Advanced systems. Unlike conventional schemes that have static resource regions for each data link, the proposed schemes dynamically allocate the resources of each link to resource blocks, by considering the channel state and the capacity of each link. We also propose resource overlapping schemes in which two different links overlap at the same resource region, so as to improve cell or user throughput performance. The proposed resource overlapping schemes do not require additional processes such as interference cancellation in users, thank to considering additional interference from resource overlapping in advance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.2
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• pp.104-110
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• 2019

In this paper, a complementary metal oxide semiconductor(CMOS) power amplifier(PA) integrated circuit operating in the 900 MHz band for long-term evolution(LTE) communication systems is presented. The output matching network based on a transformer was implemented on a printed circuit board for low loss. Simultaneously, to achieve high efficiency of the PA, the second harmonic impedances are controlled. The CMOS PA was fabricated using a $0.18{\mu}m$ CMOS process and measured using an LTE uplink signal with a bandwidth of 10 MHz and peak to average power ratio of 7.2 dB for verification. The implemented CMOS PA module exhibits a power gain of 24.4 dB, power-added efficiency of 34.2%, and an adjacent channel leakage ratio of -30.1 dBc at an average output power level of 24.3 dBm.

• Journal of the Korean earth science society
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• v.21 no.5
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• pp.503-524
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• 2000

Intercomparisons between four kinds of data have been done to estimate the accuracy of satellite observations and model reanalysis for middle and lower tropospheric thermal state over regional oceans. The data include the Microwave Sounding Units (MSU) Channel 2 (Ch2) brightness temperatures of NOAA satellites and the vertically weighted corresponding temperature of ECMWF GCM (1980-93). The satellite data for midtropospheric temperatures are MSU2 (1980-98) in nadir direction and SC2 (1980-97) in multiple scans, and for lower tropospheric temperature SC2R (1980-97). MSU2 was derived in this study while SC2 and SC2R were described in Spencer and Christy (1992a, 1992b). Temporal correlations between the above data were high (r${\ge}$0.90) in the middle and high latitudes, but low(r${\sim}$0.65) over the low latitude and more convective regions. Their values with SC2R which included the noises due to hydrometeors and surface emission were conspicuously low. The reanalysis shows higher correlation with SC2 than with MSU2 partially because of the hydrometeors screening. SC2R in monthly climatological anomalies was more sensitive to surface thermal condition in northern hemisphere than MSU2 or SC2. The first EOF mode for the monthly mean data of MSU and ECMWF shows annual cycle over most regions except the tropics. The mode in MSU2 over the Pacific suggests the east-west dipole due to the Walker circulation, but this tendency is not clear in other data. In the first and second modes for the Ch2 anomalies over most regions, the MSU and ECMWF data commonly indicate interannual variability due to El Ni${\tilde{n}$o and La Ni${\tilde{n}$a. The substantial disagreement between observations and model reanalysis occurs over the equatorial upwelling region of the western Pacific, suggesting uncertainties in the model parameterization of atmosphere-ocean interaction.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.