• Title/Summary/Keyword: 인에이블

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Efficient QCA 2-to-4 Enable Decoder Design Based on 4-Universal Gate (4-유니버셜 게이트 기반 효율적인 QCA 2-to-4 인에이블 디코더 설계)

  • Kim, Tae-Woo;Ryu, Jung Hyuk;Jo, Jeong Hoon;Park, Jong Hyuk
    • Proceedings of the Korea Information Processing Society Conference
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    • 2018.10a
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    • pp.5-7
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    • 2018
  • VLSI(Very large scale integration) 기술을 통한 트랜지스터의 소형화를 통해 CMOS 집적 회로의 성능은 지속적으로 발전해 왔다. 이와 같은 기술 발전에 따라 집적 회로를 구성하는 디지털 논리 요소 또한 진화를 하고 있다. 디코더는 부호화된 정보를 다시 부호화되기 전으로 되돌아가는 처리를 하는 디지털 논리 요소이며 컴퓨터 설계에서 많이 사용되는 핵심 요소이다. 본 논문에서는 양자점 셀룰라 오토마타(Quantum Cellular-Automata, QCA)를 사용하여 인에이블 입력을 가진 2-to-4 디코더를 제안하였다. 4-입력 유니버설 게이트의 하나의 입력을 1로 고정시켜 3-입력 NOR 게이트로 사용하며, 입력 값 X와 입력 값 Y의 중복된 배선 수를 감소시키고 한 배선으로 두 게이트에 입력을 연결하여 디코더의 배선 수와 배선 교차부를 최소화한다. 제안안하는 4-to-2 인에이블 디코더는 기존 디코더보다 셀의 개수와 클럭수를 감소시켜 디코더의 성능을 더 효율적으로 향상시켰다. 이를 통해 고속 회로 설계에 활용 및 높은 성능을 기대 할 수 있으며 QCA 연구에 기여할 수 있을 것으로 전망 한다.

A Qualitative Content Analysis on the Ablenews Reports on Personal Assistance Service Conflicts (장애인활동보조서비스 갈등에 관한 에이블뉴스 보도 내용분석)

  • Kim, Moon-geun
    • Korean Journal of Social Welfare Studies
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    • v.45 no.3
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    • pp.97-125
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    • 2014
  • The purpose of this study was to investigate the contributions and limitations of an independent internet newspaper dedicated to disability affairs. The materials analysed in this study were articles on personal assistance service conflicts between users and assistants by Ablenews. This study used inductive content analysis, responsibility frame analysis, and disability paradigm analysis. First, in general Ablenews appeared to report personal assistance service conflicts as they were. Second, the results showed that Ablenews tended to attribute the causes and solutions of the conflicts to the users and assistants. Third, nearly half of content units of Ablenews articles conveyed the perspective of rehabilitation paradigm though personal assisstanc services are closely related to independent living model. Based on the results this study suggested that Ablenews needs to improve specialty in reports on disability affairs using editorial staff, professional reporters, guests reporters with specialties.

A Low Power Realization by Eliminating Glitch-Propagation in an ALU with P/G blocks (P/G블록을 가진 ALU에서 글리치 전파제거에 의한 저전력 실현)

  • Ryu, Beom-Seon;Lee, Seong-Hyeon;Lee, Gi-Yeong;Jo, Tae-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.1
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    • pp.55-68
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    • 2001
  • This paper presents a new ALU architecture to minimize glitching power consumption which is appeared in the conventional one with P(carry propagation)/G(carry generation) blocks. In general, A lot of glitches generated once are propagating into the next stage of circuits to make unnecessary power dissipation. Therefore, a new ALU architecture which removes the glitches at the output of P/G blocks is presented in this paper. If a lot of glitches at the output of P/G blocks are removed, then the signal transitions caused by glitches are reduced in the sum generation block and hence power consumption is also reduced. A latch is inserted into the conventional P/G blocks to remove the glitches at the output of P/G blocks. Latch enable signal can make a role in eliminating a lot of glitches at the P/G's outputs by controlling output enable time. Experimental results from HSPICE simulations with implementing 16-b ALU show 28% reduction in glitching power consumption with negligible delay penalty.

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Low-Power Synchronization Technique for On-Chip Communication (온 칩 통신을 위한 저 전력 동기화 기술)

  • Lee, Jung-Hyun;Kim, Dong-Chul;Eo, Yung-Seon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.10
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    • pp.33-38
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    • 2011
  • A novel low-power synchronization technique is presented for the local synchronization. Since the proposed technique transmits an enable signal instead of a clock signal which consumes large power, it can considerably reduce the power consumption. The source-synchronization scheme which is widely adopted for the local synchronization is compared with the proposed technique. It is shown that the proposed low-power synchronization technique provides approximately 50% power saving.

Design of CMOS Temperature Sensor Using Ring Oscillator (링발진기를 이용한 CMOS 온도센서 설계)

  • Choi, Jin-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.9
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    • pp.2081-2086
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    • 2015
  • The temperature sensor using ring oscillator is designed by 0.18㎛ CMOS process and the supply voltage is 1.5volts. The temperature sensor is designed by using temperature-independent and temperature-dependent ring oscillators and the output frequency of temperature-independent ring oscillator is constant with temperature and the output frequency of temperature-dependent ring oscillator decreases with increasing temperature. To convert the temperature to a digital value the output signal of temperature-independent ring oscillator is used for the clock signal and the output signal of temperature-dependent ring oscillator is used for the enable signal of counter. From HSPICE simulation results, the temperature error is less than form -0.7℃ to 1.0℃ when the operating temperature is varied from -20℃ to 70℃.

Design and Implementation of a Single-Chip 8-Bit Microcontroller (단일 칩 8비트 마이크로컨트롤러의 설계 및 구현)

  • Ahn, Jung-Il;Park, Sung-Hwan;Kwon, Sung-Jae
    • Journal of Korea Society of Industrial Information Systems
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    • v.11 no.4
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    • pp.72-81
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    • 2006
  • In this paper, we first define a total of 64 instructions that are considered to be essential and frequently used, construct a datapath diagram, determine the control sequence using a finite state machine, and implement an 8-bit microcontroller using FPGA in VHDL. In the past, only functional simulation results of a rudimentary microcontroller were reported, the microcontroller lacked interrupt handling capability, or it was not implemented in hardware. We have designed a self-contained 8-bit microcontroller such that it can perform data transfer, addition, and logical operations, as well as stack and external interrupt operations. Following timing simulation of the designed microcontroller, we implemented it in an FPGA and verified its operation successfully. The design and implementation has been done under the Altera MAX+PLUS II integrated development environment using the EP1K50TC144-3 chip. The maximum operating frequency, the total number of logic elements used, and the logic utilization were found to be 9.39 MHz, 2813, and 97%, respectively. The result can be used as a microcontroller IP, and as needs arise, the VHDL code can be modified accordingly.

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