• Title/Summary/Keyword: 윤곽설계

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Edge Class Design for the Development of Edge-based Image Analysis Algorithm (표준화된 Edge기반 영상분석 알고리즘 개발을 위한 윤곽선 클래스 설계 및 구현)

  • 안기옥;황혜정;채옥삼
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.10b
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    • pp.589-591
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    • 2003
  • 영상에 추출된 윤곽선(Edge)은 물체의 핵심적인 형태정보를 포함하고 있어서 영상인식과 분석의 근간이 되고 있다. 따라서 정확한 윤곽선 검출을 위한 많은 연구가 진행되고 있으며 그 응용분야도 다양하다. 그러나 정작 추출된 윤곽선 정보를 효율적으로 표현하고 활용하기 위한 표준화된 자료구조에 대한 연구는 많지 않아서 연구결과의 공유를 어렵게 하고 있다. 본 논문에서는 검출된 윤곽선을 효율적으로 표현, 관리, 검색, 조작하기 위한 자료클래스를 설계구현 함으로서 윤곽선검출 알고리즘의 표준화와 재사용을 촉진시키고 검출된 다양한 응용을 가능하게 한다.

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Design of a Vision Chip for Edge Detection with an Elimination Function of Output Offset due to MOSFET Mismatch (MOSFET의 부정합에 의한 출력옵셋 제거기능을 가진 윤곽검출용 시각칩의 설계)

  • Park, Jong-Ho;Kim, Jung-Hwan;Lee, Min-Ho;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.11 no.5
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    • pp.255-262
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    • 2002
  • Human retina is able to detect the edge of an object effectively. We designed a CMOS vision chip by modeling cells of the retina as hardwares involved in edge detection. There are several fluctuation factors which affect characteristics of MOSFETs during CMOS fabrication process and this effect appears as output offset of the vision chip which is composed of pixel arrays and readout circuits. The vision chip detecting edge information from input image is used for input stage of other systems. Therefore, the output offset of a vision chip determine the efficiency of the entire performance of a system. In order to eliminate the offset at the output stage, we designed a vision chip by using CDS(Correlated Double Sampling) technique. Using standard CMOS process, it is possible to integrate with other circuits. Having reliable output characteristics, this chip can be used at the input stage for many applications, like targe tracking system, fingerprint recognition system, human-friendly robot system and etc.

공작기계의 곡선형 경로에 대한 오차모델을 이용한 제어기설계

  • 길형균;이건복
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2004.05a
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    • pp.189-189
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    • 2004
  • 본 논문은 CNC 밀링머신을 이용한 절삭가공 등 2축시스템의 위치제어 시스템을 대상으로 한다. 기존의 제어방식은 크게 독립축제어와 상호결합제어로 분류할 수 있다. 독립축제어는 두 축의 통합된 운동을 각각의 독립된 축에 대한 추적제어를 수행하여 원하는 공구경로의 위치 정밀성을 향상시키고자 하는 것이고, 상호결합제어는 지령경로에 대한 추적성능보다는 현재의 윤곽오차를 감소시키는 방향으로 제어입력을 인가하여 가공윤곽의 오차를 감소시키는데 주목적이 있다. 또한 최근의 작업공정의 고속화 경향은 윤곽오차를 감소시키면서도 추적성능이 우수한 제어방식을 요구하고 있다.(중략)

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Design of Cam Contour for Constant Hangers (등하중지지대의 캠 윤곽 설계)

  • Lee, Gun-Myung;Park, Mun-Soo
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.35 no.6
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    • pp.669-675
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    • 2011
  • A constant hanger is a device for supporting pipes in plants. It supplies a constant force to a supporting pipe even if the pipe moves because of thermal expansion. In this paper, we propose a method for designing the contour of a cam for a constant hanger. It has been shown that the contour of a cam must satisfy the geometrical relation of the cam, the force balance equation for the load tube, the relation between the side spring compression and the cam rotation angle, and the moment balance equation for the cam. A calculation procedure to solve these equations simultaneously is proposed, and a constant hanger is designed successfully.

Design and Implementation of Scaling-Invariant Boundary Image Matching System (스케일링-불변 윤곽선 이미지 매칭 시스템의 설계 및 구현)

  • Kim, Bum-Soo;Kim, Sang-Pil;Moon, Yang-Sae;Choi, Mi-Jung
    • Proceedings of the Korean Information Science Society Conference
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    • 2012.06c
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    • pp.28-30
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    • 2012
  • 본 논문에서는 시계열 매칭 기술을 활용한 스케일링-불변 윤곽선 이미지 매칭 시스템을 설계 및 구현한다. 윤곽선 이미지를 시계열로 나타낼 경우, 스케일된 유사 이미지들을 찾는데 거리 계산이 용이해지고, 인덱스 사용이 가능하여 대용량 데이터베이스 대상의 빠른 검색이 가능해지게 된다. 이를 위해, 기존연구 내용을 기반으로 사용자의 편의를 위해 GUI 환경의 클라이언트-서버 시스템으로 설계 및 구현한다. 먼저, 클라이언트에서는 사용자의 질의 이미지를 시계열로 변환하여 가로 및 세로의 스케일링 팩터구간과 허용치 ${\varepsilon}$과 함께 서버에 전달한다. 서버에서는 클라이언트에서 전달한 값들을 이용하여 범위 질의를 구성하여 이미 구축해놓은 이미지 시계열 데이터베이스의 인덱스를 통해 유사 이미지들을 찾은 후 그 결과 이미지들을 클라이언트로 전달한다. 구현 결과, 스케일링-불변 윤곽선 이미지 매칭은 직관적이고 정확한 매칭을 수행하는 것으로 나타났다.

Design of Analog CMOS Vision Chip for Edge Detection with Low Power Consumption (저전력 아날로그 CMOS 윤곽검출 시각칩의 설계)

  • Kim, Jung-Hwan;Park, Jong-Ho;Suh, Sung-Ho;Lee, Min-Ho;Shin, Jang-Kyoo;Nam, Ki-Hong
    • Journal of Sensor Science and Technology
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    • v.12 no.6
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    • pp.231-240
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    • 2003
  • The problem of power consumption and the limitation of a chip area should be considered when the pixel number of the edge detection circuit increases to fabricate a vision chip for edge detection with high resolution. The numeric increment of the unit circuit causes power consumption to increase and require a larger chip area. An increment of power consumption and a limitation of chip area with several ten milli-meters square supplied by the CMOS foundry company restrict the pixel numbers of the edge detection circuit. In this paper, we proposed a electronic switch to minimize the power consumption owing to the numeric increment of the edge detection circuit to realize a vision chip for edge detection with high resolution. We also applied a method by which photodetector and edge detection circuit are separated to implement a vision chip with a higher resolution. The photodetector circuit with $128{\times}128$ pixels uses a common edge detection circuit with $1{\times}128$ pixels so that resolution was improved at the same chip area. The chip size is $4mm{\times}4mm$ and the power consumption was confirmed to be about 20mW using SPICE.

Design and Fabrication of $8{\times}8$ Foveated CMOS Retina Chip for Edge Detection (물체의 윤곽검출을 위한 $8{\times}8$ 방사형 CMOS 시각칩의 설계 및 제조)

  • Kim, Hyun-Soo;Park, Dae-Sik;Ryu, Byung-Woo;Lee, Soo-Kyung;Lee, Min-Ho;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.10 no.2
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    • pp.91-100
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    • 2001
  • A $8{\times}8$ foveated (log-polar) retina chip for edge detection has been designed and fabricated using CMOS technology. Retina chip performs photo-input sensing, edge extraction and motion detection and we focused edge extraction. The pixel distribution follows the log-polar transform having more resolution in the center than in the periphery and can reduce image information selectively. This kind of structure has been already employed in simple image sensors for normal cameras, but never in edge detection retina chip. A scaling mechanism is needed due to the different pixel size from circumference to circumference. A mechanism for current scaling in this research is channel width scaling of MOS transistor. The designed chip has been fabricated using standard $1.5{\mu}m$ single-poly double-metal CMOS technology.

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Implementation of the adaptive Local Sigma Filter by the luminance for reducing the Noises created by the Image Sensor (이미지 센서에 의해 발생하는 노이즈 제거를 위한 영상의 조도에 따른 적응적 로컬 시그마 필터의 구현)

  • Kim, Byung-Hyun;Kwak, Boo-Dong;Han, Hag-Yong;Kang, Bong-Soon;Lee, Gi-Dong
    • Journal of the Institute of Convergence Signal Processing
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    • v.11 no.3
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    • pp.189-196
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    • 2010
  • In this paper, we proposed the adaptive local sigma filter reducing noises generated by an image sensor. The small noises generated by the image sensor are amplified by increased an analog gain and an exposure time of the image sensor together with information. And the goal of this work was the system design that is reduce the these amplified noises. Edge data are extracted by Flatness Index Map algorithm. We made the threshold adaptively changeable by the luminance average in this algorithm that extracts the edge data not in high luminance, but just low luminance. The Local Sigma Filter performed only about the edge pixel that were extracted by Flatness Index Map algorithm. To verify the performance of the designed filter, we made the Window test program. The hardware was designed with HDL language. We verified the hardware performance of Local Sigma Filter system using FPGA Demonstration board and HD image sensor, $1280{\times}720$ image size and 30 frames per second.

FPGA Implementation for Real Time Sobel Edge Detector Block Using 3-Line Buffers (3-Line 버퍼를 사용한 실시간 Sobel 윤곽선 추출 블록 FPGA 구현)

  • Park, Chan-Su;Kim, Hi-Seok
    • Journal of IKEEE
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    • v.19 no.1
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    • pp.10-17
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    • 2015
  • In this Paper, an efficient method of FPGA based design and implementation of Sobel Edge detector block using 3-Line buffers is presented. The FPGA provides the proper and sufficient hardware for image processing algorithms with flexibility to support Sobel edge detection algorithm. A pipe-lined method is used to implement the edge detector. The proposed Sobel edge detection operator is an model using of Finite State Machine(FSM) which executes a matrix mask operation to determine the level of edge intensity through different of pixels on an image. This approach is useful to improve the system performance by taking advantage of efficient look up tables, flip-flop resources on target device. The proposed Sobel detector using 3-line buffers is synthesized with Xilinx ISE 14.2 and implemented on Virtex II xc2vp-30-7-FF896 FPGA device. Using matlab, we show better PSNR performance of proposed design in terms of 3-Line buffers utilization.

Algorithm of adaptive edge enhancement to improve image visibility at mobile phone camera (모바일 폰 카메라의 이미지 선명도 향상을 위한 적응적 윤곽선 강조 알고리즘)

  • Kim, Kyung-Rin;Choi, Won-Tae;Kang, Bong-Soon
    • Journal of the Institute of Convergence Signal Processing
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    • v.9 no.4
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    • pp.288-294
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    • 2008
  • In this paper, we proposed an algorithm of edge enhancement to improve image visibility of mobile phone camera. For naturally edge enhancement, we grasps edge characteristic in image and applied to the most appropriate enhancement value adaptively about each characteristics. Namely, It applies 2D high pass filter where in the edge characteristics which judge in the first In compliance with the edge condition which is subdivided more with secondary it will be able to apply the process which able to adaptive edge enhancement to improve image visibility. It joins in and it is an existing algorithm that simply a lies 2D high pass filter where and it is identical in the image whole it will be able to improve the side effects of ringing actual condition etc. It considers the effectiveness of the hardware resource with the hardware of the algorithm which is developed and algorithm the maximum simply, it developed and simulation of the algorithm which is proposed it led and algorithm of existing and it compared and is improved the result which it confirmed.

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