• Title/Summary/Keyword: 위상 조정

Search Result 256, Processing Time 0.024 seconds

Level Set Based Shape Optimization of Linear Structures using Topological Derivatives (위상민감도를 이용한 선형구조물의 레벨셋 기반 형상 최적설계)

  • Yoon, Minho;Ha, Seung-Hyun;Kim, Min-Geun;Cho, Seonho
    • Journal of the Computational Structural Engineering Institute of Korea
    • /
    • v.27 no.1
    • /
    • pp.9-16
    • /
    • 2014
  • Using a level set method and topological derivatives, a topological shape optimization method that is independent of an initial design is developed for linearly elastic structures. In the level set method, the initial domain is kept fixed and its boundary is represented by an implicit moving boundary embedded in the level set function, which facilitates to handle complicated topological shape changes. The "Hamilton-Jacobi(H-J)" equation and computationally robust numerical technique of "up-wind scheme" lead the initial implicit boundary to an optimal one according to the normal velocity field while minimizing the objective function of compliance and satisfying the constraint of allowable volume. Based on the asymptotic regularization concept, the topological derivative is considered as the limit of shape derivative as the radius of hole approaches to zero. The required velocity field to update the H-J equation is determined from the descent direction of Lagrangian derived from optimality conditions. It turns out that the initial holes are not required to get the optimal result since the developed method can create holes whenever and wherever necessary using indicators obtained from the topological derivatives. It is demonstrated that the proper choice of control parameters for nucleation is crucial for efficient optimization process.

40Gb/s Clock and Data Recovery Circuit with Multi-phase LC PLL in CMOS $0.18{\mu}m$ (LC형 다중 위상 PLL 이용한 40Gb/s $0.18{\mu}m$ CMOS 클록 및 데이터 복원 회로)

  • Ha, Gi-Hyeok;Lee, Jung-Yong;Kang, Jin-Ku
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.45 no.4
    • /
    • pp.36-42
    • /
    • 2008
  • 40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).

Spatial - Frequency Analysis of time-varying Coherence using ERP signals for attentional visual stimulus (시각 자극의 집중에 따른 시간 변화에 대한 뇌 유발전위의 공간 - 주파수간 상관 변화 분석)

  • Lee, ByuckJin;Yoo, Sun-Kook
    • Science of Emotion and Sensibility
    • /
    • v.16 no.4
    • /
    • pp.527-534
    • /
    • 2013
  • In this study, we analyzed spatial-frequency relationship related brain function for change of the time during attentional visual stimulus through the analysis of Coherence. With experimentation about ERP(Event Related Potential)data, it revealed that change of the phase synchronization between different scalp locations at ${\theta}$, ${\alpha}$ band. ERP between left and right frontal lobes, between the frontal and central lobes showed the phase synchronization at the P100, N200, ERP between the frontal and occipital lobes showed the phase synchronization at the P300 related information of visual stimulus. Compared to STFT using the window of a fixed length, CWT is able to multi-resolution analysis with the adjustment of parameters of mother wavelet. Thus, coherence results with CWT was found to be effective for analysis of time-varying spatial-frequency relationship in ERP. The phase synchronization for inattentional visual stimulus was not observed.

Study on the Beam Pattern Compensation with Planar Active Phased Array Antenna (평면형 능동위상 배열안테나 빔 패턴 보상에 관한 연구)

  • Chon, Sang-Mi;Na, Hyung-Ki;Ahn, Chang-Soo;Kim, Seon-Joo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.25 no.2
    • /
    • pp.217-222
    • /
    • 2014
  • This paper discusses about the beam pattern distortion caused by the failures of some antenna modules in the active array antenna and analyses the possibility of improvement through applying the beam pattern compensation method previously studied. The beam pattern distortion which is mostly represented as an increase of the sidelobe level, can be suppressed through re-synthesizing each module's magnitude and phase. This method was applied to the prototype of active array antenna system, and the results of antenna pattern distortion and compensation were analyzed and measured in the Near Field Chamber. Array failures are generally divided into random TR module failures and TRU(TR Unit: combination of TR modules, Beam Computation module, Power supply module) failures. The results of beam pattern compensation were analyzed in each failure and compared to the results of the simulation. The beam pattern compensation results applied to the real active antenna array system showed the similar to the simulation results. Consequently, it was verified the beam pattern could be compensated with the magnitude and phase adjustment of other normal antenna modules.

A Design on High Frequency CMOS VCO for UWB Applications (UWB 응용을 위한 고주파 CMOS VCO 설계 및 제작)

  • Park, Bong-Hyuk;Lee, Seung-Sik;Choi, Sang-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.18 no.2 s.117
    • /
    • pp.213-218
    • /
    • 2007
  • In this paper, we propose the design and fabrication on high frequency CMOS VCO for DS-UWB(Direct-Sequence Ultra-WideBand) applications using 0.18 ${\mu}m$ process. The complementary cross-coupled LC oscillator architecture which is composed of PMOS, NMOS symmetrically, is designed for improving the phase noise characteristic. The resistor is used instead of current source that reduce the 1/f noise of current source. The high-speed buffer is needed for measuring the output characteristic of VCO using spectrum analyzer, therefore the high-speed inverter buffer is designed with VCO. A fabricated core VCO size is $340{\mu}m{\times}535{\mu}m$. The VCO is tunable between 7.09 and 7.52 GHz and has a phase noise lower than -107 dBc/Hz at 1-MHz offset over entire tuning range. The measured harmonic suppression is 32 dB. The VCO core circuit draws 2.0 mA from a 1.8 V supply.

On-Line Social Network Generation Model (온라인 소셜 네트워크 생성 모델)

  • Lee, Kang-Won
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.24 no.7
    • /
    • pp.914-924
    • /
    • 2020
  • In this study we developed artificial network generation model, which can generate on-line social network. The suggested model can represent not only scale-free and small-world properties, but also can produce networks with various values of topological characteristics through controlling two input parameters. For this purpose, two parameter K and P are introduced, K for controlling the strength of preferential attachment and P for controlling clustering coefficient. It is found out on-line social network can be generated with the combinations of K(0~10) and P(0.3~0.5) or K=0 and P=0.9. Under these combinations of P and K small-world and scale-free properties are well represented. Node degree distribution follows power-law. Clustering coefficients are between 0.130 and 0.238, and average shortest path distance between 5.641 and 5.985. It is also found that on-line social network properties are maintained as network node size increases from 5,000 to 10,000.

Study on Construction of Transportation/Road Framework Data (교통/도로 기본지리정보 구축에 관한 연구)

  • Yoo, Hwan Hee;Kim, Eui Myoung;Kim, Sung Sam;Cho, Jung Un
    • Journal of Korean Society for Geospatial Information Science
    • /
    • v.9 no.1 s.17
    • /
    • pp.27-38
    • /
    • 2001
  • The GIS construction project using the Digital Map has been progressed actively since the enforcement of NGIS project in 1995. But, the Digital Map actually can't use directly in building GIS because of many defects of the digital map such as geometric features errors(the overshoot/undershoot of line or the opening of polygon), non-topology etc. Many advanced countries in GIS has provided users Framework Data which is generated topology defined spatial relationships and used as a basic data of national geospatial information. In this study, we proposed the definition and the scope of Framework Data as a basemap of the Nation Geospatial Information and studied for the management and construction of the Transportation/Road Framework Data which is a core and basic data among them.

  • PDF

Minimum-Entropy-Based Autofocus Method for Real SAR Images (실제 SAR 영상에서의 최소 엔트로피 기반의 자동 초점 기법 연구)

  • Hwang, Jeonghun;Shin, Hyun-Ik;Kim, Whan-Woo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.29 no.5
    • /
    • pp.366-374
    • /
    • 2018
  • In cases of airborne equipped with SAR, because the occurrence of motion is inevitable, it is necessary to apply autofocus techniques to SAR images to improve the image performance degradations caused by residual errors. Herein, a robust autofocus algorithm based on the minimum entropy criteria is proposed for the real SAR data in the spotlight mode. The convergence condition of the phase error estimation is checked at every iteration and if it is violated, the size of the phase error estimation is adjusted to the convergence condition. The real SAR raw data is used to demonstrate the excellent performance of the proposed algorithm.

Performance Improvement of Controller using Fuzzy Inference Results of System Output (시스템 출력의 퍼지추론결과를 이용한 제어기의 성능 개선)

  • 이우영;최홍문
    • Journal of the Korean Institute of Intelligent Systems
    • /
    • v.5 no.4
    • /
    • pp.77-86
    • /
    • 1995
  • The new architecture that fuzzy logic control(FLC) with difficulties for tuning membership function (MF) is parallel with neural networks(NN) to be learned from the output of FLC is proposed. Therefore proposed scheme has the characteristics to utilize the expert knowledge in design process, to be learned during the operation without any learning mode. In this architecture, the function of the FLC is to supply the sliding surface which is constructed on the phase plane by rule base for giving the desired control characteristics and learning criterion of NN and the stabilization of the control performance before NN is learned, The function of the NN is to let the system trajectory be tracked to the sliding surface and reached to the stable point.

  • PDF

Development of Base station Antenna Using Phased Away Technology (위상배열 안테나 기술을 적용한 기지국용 안테나 개발)

  • Lee, Chang-Eun;Yun, Jong-Sup;Moon, Young-Chan;Hur, Jung
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.41 no.5
    • /
    • pp.77-83
    • /
    • 2004
  • Based on a Phased array technology, 2-dimensionally steerable base station antenna was developed at cellular band. The antenna, which consists of 2 by 5 radiating element, can provide 14㏈i gain with half power beam width of 0$^{\circ}$and 13$^{\circ}$ in horizontal and vertical plane respectively. It has beam scanning range of 0$^{\circ}$to 12$^{\circ}$in vertical down tilting and -15$^{\circ}$to 15$^{\circ}$in horizontal steering. The beam control Performance of antenna was verified by DM measurement on field trial.