• Korean Journal of Optics and Photonics
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• v.10 no.6
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• pp.507-511
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• 1999

A 10 GHz timing extracted signal which is phase-locked to a 10 Gbit/s mode-locked optical fiber laser pulse train is obtained using a tour-wave-mixing signal in semiconductor optical amplifier. The phase-locked loop wm, demonstrated ~Llccessful1y over 8 hours and found to have the lock-in frequency range of 30 KHz. 0 KHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1464-1474
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• 1994

GPS(Global Positioning System)is a satellite-based navigation system that we can survey where we are, anywhere and anytime. In this paper, delay-lock loop of the receiver which detects the navigation data is theoretically analyzed, and designed using the digital logic circuit. Also logic operations for the synchronization are analyzed. The designed system consists of the correlator which correlates the received C/A code and the generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock syntheizer which generates the clock of the C/A code generator to control the C/A code phase and clock rate. From the analyses results of the proposed digital delay-lock loop system, the system has the detection propertied over 90% when its input signal power is above-113.98dB. The influence of input signal variation of digital delay loop, which is the input of A/D converter, is investigated and the performance is analyzed with the variation of threshold level via the computer simulation. The logic simulation results show that the designed system detects precisely the GPS navigation data.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.967-973
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• 2009

In this paper, X-band satellite communication oscillator of double phase locked is implemented by constructing a couple of phased-locked loop, and then we have analyzed the phase noise of designed PLL-DRO. The designed phase-locked oscillator is consist of series feedback DRO, frequency divider, phase detector, loop filter and programmable PLL-IC. By dividing oscillation frequency of 12.6 GHz into two frequencies, it exhibits output power of 15.32 dBm at 6.3 GHz. Phase noises of implemented oscillator are -81 dBc/Hz@100Hz, -100.86 dBc/Hz@1 kHz, -111.12 dBc/Hz@10 kHz, -116 dBc/Hz@100 kHz and -140.49 dBc/Hz@1 MHz respectively. These indicate excellent stable operation of oscillator and very good phase noise characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.11a
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• pp.243-247
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• 1998

SO(Synchronous Oscillator)는 동기, 동조, 필터, 증폭, 분주를 하나의 과정으로 처리할 수 있는 회로망이며, CPSO(Coherent Phase Synchronous Oscillator)는 50에 2개의 외부 루프를 첨가함으로서 구성되며, SO의 모든 장점을 유지하면서 동조범위 안에서 위상차가 없는 것이 큰 특징이다. 본 논문에서는 CPSO의 이러한 성질을 이용하여 GPS (Global Positioning System)에서 많이 사용하고 있는 부호동기방식인 DLL(Delay Lock Loop)과 TDL(Tau dither Loop)을 대치할 수 있는, 회로가 간단하고 추적범위가 넓으며 동기가 용이한 CPSO를 GPS의 부호동기 시스템에 적용하였다.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.435-438
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• 2006

위성신호는 저앙각에 위치하거나 재밍 및 간섭신호의 영향을 받으면 약해진다. 이러한 약신호를 안정적으로 추적하기 위해서는 신호추적루프의 대역폭이 가능하면 작아야 한다. 그러나 작은 대역폭의 신호추적루프는 고기동 환경에서 기준주파수의 주파수오차를 포함한 입력오차가 커져 불안정해진다. 본 논문에서는 최대 저크 15g/s의 동적특성을 가지는 항체의 항법정보를 획득하고 동시에 28dB-Hz의 약신호도 안정적으로 추적할 수 있는 신호추적루프를 연구한다. 이를 위해 위성신호 상태를 예측할 수 있는 SNR, 앙각, 항체의 가속도 등을 고려하여 대역폭 및 PIT를 가변적으로 설계한 적응형 신호추적루프를 설계한다. 또한 약신호인 C/No 28dB-Hz 신호를 안정적으로 추적하기 위해 10ms의 PIT(Predetection Integration Time)와 비트동기를 고려한 Coherent 방식을 적용한 반송파 위상추적루프를 설계한다. 이렇게 설계된 신호추적루프의 성능을 검증하기 위해 항체의 동적환경과 위성신호 크기를 묘사해줄 수 있는 시뮬레이터를 이용하여 위성신호 추적성능을 시험하고 결과를 분석한다.

• Proceedings of the KIEE Conference
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• 2006.04b
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• pp.223-225
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• 2006

본 논문에서는 매입형 영구자석 동기전동기(IPMSM)의 속도추정을 위한 새로운 센서리스 알고리즘을 제안한다. 매입형 영구자석 동기 전동기의 기본 전압 방정식을 이용하여 회전자의 자속을 추정하고, 위상고정루프(PLL)를 사용하여 회전자의 위치와 속도를 추정하는 방법으로 센서리스 알고리즘을 구성하였다. Matlab SIMULINK를 이용한 시뮬레이션과 실험을 통하여 제안된 알고리즘을 검증하였다.

• The KIPS Transactions:PartC
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• v.11C no.6 s.95
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• pp.835-842
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• 2004

In this paper, we have analyzed the MC-DS/CDMA system with input signal synchronized completely through adjustment of the gain in the PLL loop, by using the hybrid SC/MRC-(2/3) technique, which is said to one of the optimal diversity techniques under the multi-path fading environment, assuming that phase error is defined to the phase difference between the received signal from the multi-path and the reference signal in the PLL of the receiver. Also, assuming that the regarded radio channel model for the mobile communication is subject to the Nakagami-m fading channel, we have developed the expressions and performed the simulation under the consideration of various factor, in the MC/DS-CDMA system with the hybrid SC.MRC-(2/3) diversity method, such as the Nakagami fading index(m), $the\;number\;of\;paths\;(L_p),$ the number of hybrid SC.MRC-(2/3) $diversity\;branches\;(L,\;L_c),$ the number of users (K), the number of subcarriers (U), and the gain in the PLL loop. As a result of the simulation, it has been confirmed that the performance improvement of the system can be achieved by adjusting properly the PLL loop in order for the MC/DS-CDMA system with the hybrid SC/MRC-(2/3) diversity method to receive a fully synchronized signal. And the value of the gain in the PLL loop should exceed 7dB in order for the system to receive the signal with prefect synchronization, even though there might be a slight difference according to the values of the fading index and the spread processing gain of the subcarrier.

• The Journal of the Acoustical Society of Korea
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• v.29 no.4
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• pp.229-236
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• 2010

Phase coherent modulation techniques in underwater acoustic channel can improve bandwidth efficiency and data reliability, but they are made difficult by time-varying intersymbol interference. This paper proposes an adaptive equalizer combined with phase estimator which compensates distortions caused by time-varying multipath and phase variation. The experiment in the East sea demonstrates phase coherent signals are distorted by time-varying multipath propagation and the proposed scheme equalizes them. Bit error rate of BPSK and QPSK are 0.0078 and 0.0376 at 300 meter horizontal distance and 0.0146 and 0.0293 at 1000 meter respectively.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.52-59
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• 1998

New types of PFD (phase-frequency detector) are proposed with reset time and propagation delay reduced. The perfomrance of our proposed PFDs are confirmed by SPICE simulation with 0.8.mu.m CMOS process parameter. As a result of simulation, the reset time of PFDs are 0.32 nsec and 0.030 nsec in capture-process. The proposed PFDs can be used in hihg-speed phase-licked loop (PLL).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1774-1781
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• 1997

In this paper, we propose a full digital frequency and phase locked loop for CATV and HDTV receivers adopting VSB modulation. The CATV and HDTV receivers proposed by the Grand-Alliance in USA are ultilizing analog signal processing technology for carrier recovery. By the way, it is not a good architecture for the development of single chip ASIC operating in digital domain. To solve this problem while improving the performance, we first down convert the received r.f. signal to a near baseband signal for a low-rate AD converter and then we use digital signal processing techniques. The proposed system has the frequency pull-in range of -200 KHz +2.50 KHz. Moreover, it has the ability of adaptive loop bandwidth control according to the amount of frequency offset to improve the acquisition time while reducing the phase noise.