• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.7
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• pp.597-605
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• 2015

Negative impedance converter(NIC)-based non-Foster impedance matching is proposed for an electrically small antenna. The antenna considered in this work is a resistively loaded vee dipole(RVD) antenna, which has considerable reflection at the feed point because of its large negative input reactance. The non-Foster matching circuit built near the feed point consists of two-stage NIC circuit and a capacitor connected between the stages. The NIC is realized by using operational amplifiers(op-amps) and resistors. The circuit is designed by considering of the input impedance according to the finite open-loop gain of the practical NICs. The stability test of the impedance-matched RVD antenna is performed. The non- Foster matching circuit is implemented with the RVD antenna. The measured impedance demonstrates that the proposed non-Foster matching circuit effectively reduces the input reactance of the RVD antenna.

• Journal of KIISE:Software and Applications
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• v.36 no.7
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• pp.590-606
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• 2009

We present a static analyzer that detects memory leaks in C programs. It achieves relatively high accuracy at a relatively low cost on SPEC2000 benchmarks and several open-source software packages, demonstrating its practicality and competitive edge against other reported analyzers: for a set of benchmarks totaling 1,777 KLOCs, it found 332 bugs with 47 additional false positives (a 12.4% false-positive ratio), and the average analysis speed was 720 LOC/sec. We separately analyze each procedure's memory behavior into a summary that is used in analyzing its call sites. Each procedural summary is parameterized by the procedure's call context so that it can be instantiated at different call sites. What information to capture in each procedural summary has been carefully tuned so that the summary should not lose any common memory-leak-related behaviors in real-world C program. Because each procedure is summarized by conventional fixpoint iteration over the abstract semantics ('a la abstract interpretation), the analyzer naturally handles arbitrary call cycles from direct or indirect recursive calls.

• Journal of Platform Technology
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• v.8 no.1
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• pp.24-32
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• 2020

This paper designed and manufactured a chip mounter based on 3D printer technology that can be used for educational research or sample production to disseminate chip mounter, a core technology of SMT line. A stepper motor with open loop control is used for low cost drive design. The shortcomings of the motor's vibration and disassembly caused by the use of the step motor were compensated by the Micro-Step control method. In the chip mounter experiment, the gerber file was generated on the small chip mounter, printed at the actual size, and the solder cream was printed on the HASL-treated PCB in the same manner as the sample board fabrication. As a result of the experiment, unlike the 2012 micro components, parts such as SOIC and TQFP that require correction are twice as long as the component mounting time, but it can be confirmed that they are mounted relatively accurately. In addition, as a result of repeatedly measuring the error of the initial position 10 times, it was confirmed that a relatively small error of about 0.110mm occurs.

• Fire Science and Engineering
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• v.34 no.2
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• pp.86-93
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• 2020

This study aims to maintain the safety of an outdoor storage tank through the fundamental case analysis of explosion and fire accidents in the storage tank. We consider an accident caused by the explosion of fire inside the tank, as a result of the gradual spreading of the residual fire generated by wind lamps flying off a workplace in the storage tank yard. To determine the cause of the accident, atmospheric diffusion conditions were derived through CCTV image analysis, and the wind direction was analyzed using computational fluid dynamics. Additionally, the amount of oil vapor inside the tank when the floating roof was at the lowest position, and the behavior of the vapor inside the tank when the floating roof was at the highest position were investigated. If the cause of the explosion in the storage tank is identified and the level of the storage tank is maintained below the internal floating roof, dangerous liquid fills the storage tank, and the vapor in the space may stagnate on the internal floating roof. We intend to improve the operation procedure such that the level of the storage tank is not under the Pontoon support, as well as provide measures to prevent flames from entering the storage tank by installing a flame arrester in the open vent of the tank.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.53-60
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• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Journal of Broadcast Engineering
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• v.28 no.1
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• pp.145-148
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• 2023

Open-loop Octonion space-time block code for 4 transmit antenna system is considered and random phases are applied to 4 transmit antennas for physical layer security. When an illegal hacker estimates the random phases of 1 through 4 transmit antennas with maximum likelihood (ML), this letter analyzes the bit error rate (BER) performances versus signal-to-noise ratio (SNR). And the Octonion code in the literature[1] does not have full orthogonality so, this letter employs the perfect orthogonal Octonion code. When the hacker knows that the random phases are 2-PSK constellations and he should estimate all the 4 random phases, the hacking is impossible until 100dB. When the hacker possibly know that some of the random phases, bit error rate goes down to 10^-3 so, the transmit message could be hacked.