• Journal of Advanced Navigation Technology
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• v.16 no.6
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• pp.1032-1037
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• 2012

Augmented reality (AR) is augmented virtual information on the real world with real-time. And user can interact with information. In this paper, Marker-less tracking algorithm has been studied, for implement the augmented reality system on a mobile environment. In marker-less augmented reality, users do not need to attach the markers, and constrained the location. So, it's convenient to use. For marker-less tracking, I use the SURF algorithm based on feature point extraction in this paper. The SURF algorithm can be used on mobile devices because of the computational complexity is low. However, the SURF algorithm optimization work is not suitable for mobile devices. Therefore, in this paper, in order to the suitable tracking in mobile devices, the SURF algorithm was tested in a variety of environments. And ways to optimize has been studied.

• Journal of Internet Computing and Services
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• v.14 no.1
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• pp.53-62
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• 2013

It is common among users to have multiple computing devices as well as to access their files or do work at different locations. To achieve file consistency as well as mobility in this scenario, an efficient approach for workspace synchronization should be used. However, file synchronization alone cannot guarantee the mobility of work environment which allows activities to be resumed at any place and time. This paper proposes a ubiquitous synchronization approach which provides cloud-based access to a user's workspace. Efficient synchronization is achieved by combining session monitoring with file system management. Experimental results show that the proposed mechanism outperforms Cloud Master-replica Synchronization in terms of number of I/O operations, CPU utilization, as well as the average and maximum latencies in responding to client requests.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.42-49
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• 2007

CABAC(Context-based Adaptive Binary Arithmetic Coding) among various entropy coding schemes which are used to improve compression efficiency in H.264/AVC has a high hardware complexity and the fast calculation is difficult because data dependancy exists in the bit-serial process. In this paper, the proposed architecture efficiently compose the renormalization process of binary arithmetic encoder which is an important part of CABAC used in H.264/AVC. At every clock cycle, the input symbol is encoded regardless of the iteration of the renormalization process for every input symbol. Also, the proposed architecture can deal with the bitsOutstanding up to 127 which is adopted to handle the carry generation problem and encode input symbol without stall. The proposed architecture with three-stage pipeline has been synthesized using the 0.18um Dongbu-Anam standard cell library and can be operated at 290MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.1
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• pp.71-77
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• 2005

In this paper we implement a headphone-based 5.1 channel 3-dimensional (3D) sound generation system using HRTF (Head Related Transfer Function). Each mono sound source in the 5.1 channel signal is localized on its virtual location by binaural filtering with corresponding HRTFs, and reverberation effect is added for spatialization. To reduce the computational burden, we reduce the number of taps in the HRTF impulse response and model the early reverberation effect with several tens of impulses extracted from the whole impulse sequences. We modified the spectrum of HRTF by weighing the difference of front-back spec01m to reduce the front-back confusion caused by non-individualized HRTF DB. In informal listening test we can confirm that the implemented 3D sound system generates live and rich 3D sound compared with simple stereo or 2 channel down mixing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.66-74
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• 2001

In this paper, we proposed the new structure of the Rake Finger using Walsh Switch, the shared accumulator, and the pipeline FWHT(Fast Walsh Hadamard Transform) algorithm for reducing the signal processing complexity resulting from the increase of the number of data correlators. The function simulation of the proposed architecture is performed by Synopsys tool and the timing simulation is performed by Compass tool. The number of computational operation in the proposed data correlators is 160 additions and the conventional ones is 512 additions when the number of walsh code channels is 4. As a result, it is reduced about 3.2 times other than the number of computational operation of the conventional ones. Also, the result shows that the data processing time of the proposed Rake Finger architecture is 90,496[ns] and the conventional ones is 110,696[ns]. It is 18.3% faster than the data processing time of the conventional Rake Finger architecture.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.6
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• pp.94-102
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• 2009

In [1], the authors have proposed a novel scheme to achieve full diversity and to combat the time delays from each relay node, but decode-and-forward (DF) model operation mode puts more processing burden on the relay. In this paper, we not only extend their model into amplify and forward (AF) model proposed in [2],[3], but also propose an efficient decoding algorithm, which is able to order the joint channel coefficients of overall channel consisting of source-relay link and relay-destination link and cancels the previous decoded symbols at the next decoding procedure. The simulation results show that this algorithm efficiently improves its performance achieving 2-3dB gain compared to [1] in high SNR region and also useful to DF achieving more than 3dB gain compared to an original algorithm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.2
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• pp.62-68
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• 2007

This paper proposes an efficient integer division algorithm for high speed FPGAs' which support built-in RAMs' and multipliers. The integer division algorithm is iterative with RAM-based LUT and multipliers, which minimizes the usage of logic fabric and connection resources. Compared with some popular division algorithms such as division by subtraction or division by multiply-subtraction, the number of iteration is much smaller, so that very low latency can be achieved with pipelined implementations. We have implemented our algorithm in the Xilinx virtex-4 FPGA with VHDL coding and have achieved 300MSPS data rate in 17bit integer division. The algorithm used less than 1/6 of logic slices, 1/4 of the built-in multiply-accumulation units, and 1/3 of the latencies compared with other popular algorithms.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.13-19
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• 2020

In this paper, we propose a multiplexer based scheme that performs modular AB² multiplication using redundant basis over finite field. Then we propose an efficient multiplexer based semi-systolic AB² multiplier using proposed scheme. We derive a method that allows the multiplexers to perform the operations in the cell of the modular AB² multiplier. The cell of the multiplier is implemented using multiplexers to reduce cell latency. As compared to the existing related structures, the proposed AB² multiplier saves about 80.9%, 61.8%, 61.8%, and 9.5% AT complexity of the multipliers of Liu et al., Lee et al., Ting et al., and Kim-Kim, respectively. Therefore, the proposed multiplier is well suited for VLSI implementation and can be easily applied to various applications.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.4
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• pp.165-172
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• 2002

In the next generation mobile communications, powerful channel coding is essential in order to obtain high quality multimedia services. Turbo code can achieve good error performance by iterative decoding, but more iterations result in additional computational complexity and delay. Thus, a method to reduce the number of iterations without additional performance degradation is needed. Turbo code with CRC is known to be the most efficient method to reduce the number of iterations. In this scheme, the performance may be degraded by the edge-effect like the conventional turbo code without CRC. In this paper, a method to eliminate the edge-effect is proposed by adopting D-parameter to the conventional s-random interleaver. As results of simulation, the edge-effect of the turbo code with CRC is shown to be successfully eliminated by using the new interleaver designed with D-parameter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.12
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• pp.2315-2320
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• 2006

A real-time frame-layer rate control algorithm with a token bucket traffic shaper is proposed for low bit rate video coding. The proposed rate control method uses a non-iterative optimization method for low computational complexity, and performs bit allocation at the frame level to minimize the average distortion over an entire sequence as well as variations in distortion between frames. In order to reduce the quality fluctuation, we use a sliding window scheme which does not require the pre-analysis process. Therefore, the proposed algorithm does not produce time delay from encoding, and is suitable for real-time low-complexity video encoder. Experimental results indicate that the proposed control method provides better visual and PSNR performances than the existing rate control method.