• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.1
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• pp.79-85
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• 2005

In this paper, low-power design and implementation techniques for IMT-2000 interpolation filter are proposed. Processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized for low-power implementation. proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of filter coefficient. Finally, in third shift register block, multiplied values are output and stored in shift register. For IMT-2000 interpolation filter, proposed and conventional structures are implemented by using Verilog-HDL coding. Gate counts for the proposed structure is reduced to 31.57% comparison with those of the conventional one.

• The Journal of Korean Association of Computer Education
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• v.11 no.1
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• pp.97-107
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• 2008

The result verification that determines correctness for the work results calculated in each PC is one of the most important issues in PC grid environments. In this literature, voting-based and trust-based schemes have been mainly used to guarantee the correctness of work results. However, these schemes suffer from both waste of resource utilization and high computation delay because they can not effectively cope with dynamic computational environments. To overcome these shortcomings, we introduce the distribution information of PC resources based on credibility and availability into result verification phase. Using this information, we propose a new result verification scheme, which can determine the correctness of work results by each PC resources' credibility and cope with the dynamic changing environments by each PC resources' availability. To demonstrate the efficiency of our result verification scheme, we evaluate the performance of our scheme from the viewpoints of turnaround time and resource utilization, utilizing resource distribution information in the Korea@Home that is a representative PC grid system in domestic. We also compare the performance of our scheme with that of other ones.

• The KIPS Transactions:PartD
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• v.10D no.4
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• pp.647-654
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• 2003

The replication of data is used to increase its availability and to improve the performance of a system. The distributed database system has to maintain both the database consistency and the replica consistency. This paper proposes an algorithm which resolves the conflict of the operations by using the mechanism based on the structure that the replicas of each data item are hierarchically organized. Each update is propagated along the tree based on the fact that the root of each data item is the primary replica in partially replicated databases. The use of a hierarchy of data may eliminate useless propagation since the propagation can be done only to sites having the replicas. In consequence, the propagation delay of updates may be reduced. By using the timestamp and a compensating transaction, our algorithm resolves the non-serializability problem caused by the conflict of operations that can happen on the way of the update propagation due to the lazy propagation. This resolution also guarantees the data consistency.

• Journal of Korean Society of Environmental Engineers
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• v.28 no.1
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• pp.97-103
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• 2006

In this paper, a control method of a mini ozone generator is proposed, and also a cooling technique is described which is cooling down the flowing air gap into a silent discharger to $2^{\circ}C$ to generate ozone of high density and diffusing power. As the digital control system for this method, a double feedback loop is designed which detects the voltage and current of equivalent capacitor of the discharger and compensates for the poor power waveform caused by the noise at high discharging frequency. During the plant modeling of this system, computing time factor is considered as a unique parameter of the power system to improve the transient responses with regard to fluctuating load and to replenish the computing time delay of the controller. Through the experiment, sinusoidal input current for discharger can be acquired and all the effectiveness of this accurate control system over unstable ozone discharger are proved.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.943-949
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• 2010

This paper presents some improvements on VLSI implementation of lifting-based 9/7 wavelet transform by optimization hardware multiplication. The proposed solution requires less logic area and power consumption without performance loss compared to previous wavelet filter structure based on lifting scheme. This paper proposes a better approach to the hardware implementation using Lefevre algorithm based on extensions of Pattern search methods. To compare the proposed structure to the previous solutions on full multiplier blocks, we implemented them using Verilog HDL. For a hardware implementation of the two solutions, the logical synthesis on 0.18 um standard cells technology show that area, maximum delay and power consumption of the proposed architecture can be reduced up to 51%, 43% and 30%, respectively, compared to previous solutions for a 200 MHz target clock frequency. Our evaluation show that when design VLSI chip of lifting-based 9/7 wavelet filter, our solution is better suited for standard-cell application-specific integrated circuits than prior works on complete multiplier blocks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.123-130
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• 2004

This paper describes a multiplier architecture optimized for 32 bit RISC processor with 3-stage pipeline. The multiplier of ARM7, the target processor, is variably carried out on the execution stage of pipeline within 7 cycles. The included multiplier employs a modified Booth's algerian to produce 64 bit multiplication and addition product and it has 6 separate instructions. We analyzed several multiplication algorithm such as radix4-32${\times}$8, radix4-32${\times}$16 and radix8-32${\times}$32 to decide which multiplication architecture is most fit for a typical architecture of ARM7. VLSI area, cycle delay time and execution cycle number is the index of an efficient design and the final multiplier was designed on these indexes. To verify the operation of embedded multiplier, it was simulated with various audio algorithms.

• The Journal of the Acoustical Society of Korea
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• v.31 no.2
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• pp.79-86
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• 2012

In this paper, we propose an enhanced algorithm for affine projection algorithms which have been proposed to speed up the convergence of the conventional NLMS algorithm. Since affine projection (AP) or pseudo AP algorithms are based on the delayed input vector and error vector, they are complicated and not suitable for applying methods developed for the LMS-type algorithms which are based on the scalar error signal. We devised a variable step size algorithm for pseudo AP using the fact that pseudo AP algorithms are updated using the scalar error and that the error signal is getting orthogonal to the input signal. We carried out a performance comparison of the proposed algorithm with other pseudo AP algorithms using a system identification model. It is shown that the proposed algorithm presents good convergence characteristics under both stationary and non-stationary environments despites its low complexity.

• Journal of IKEEE
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• v.19 no.1
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• pp.87-93
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• 2015

In this paper, a $145{\mu}W$, 87dB SNR, Low power 3rd order Sigma-Delta Modulator with Op-amp sharing is proposed. Conventional architecture with analog path and digital path is improved by adding a delayed feed -forward path for disadvantages that coefficient value of the first integrator is small. Proposed architecture has a larger coefficient value of the first integrator to remove the digital path. Power consumption of proposed architecture using op-amp sharing is lower than conventional architecture. Simulation results for the proposed SDM designed in $0.18{\mu}m$ CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and sampling frequency 2.8224MHz shows SNR(Signal to Noise Ratio) of 87dB, the power consumption of $145{\mu}W$.

• Journal of KIISE:Databases
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• v.29 no.3
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• pp.159-167
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• 2002

Recently, a major issue in the research of metadata is the standardization of metadata format. The new extension capability of metadata in the standardization requires some changes - storing and managing dynamic data consistently. In this paper, we define the characteristics of new metadata and propose a concurrency control called Two Version Latch (2VL). 2VL uses a latch and maintains two versions. Maintaining two versions using latch minimizes conflicts between read operation and write operation. The removal of unnecessary lock holding minimizes refresh latency. Therefore, this algorithm presents fast response time and recent data retrieval in read operation execution. As a result of the performance evaluation, the 2VL algorithm is shown to be better than other algorithms in metadata management system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9C
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• pp.771-777
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• 2010

This paper proposes a new signal detection method, called QR-OSIC with Candidates (QOC) method, for spatially multiplexed multiple input multiple output (MIMO) systems. By using the ordered successive interference cancellation (OSIC) algorithm and the maximum likelihood (ML) metric, the proposed method achieves near-ML performance without requiring a large number of candidates. Although the proposed method can be used for both hard and soft decoding systems, it is especially useful for soft decoding systems since the LLR values for all the bits can be efficiently computed without using LLR estimation. The proposed method is also suitable for VLSI implementation since it leads to fixed throughput system.