• Journal of IKEEE
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• v.19 no.3
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• pp.378-384
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• 2015

In conventional HEVC inverse core transform architectures, extra $n{\times}n$ inverse transform block is added to $2n{\times}2n$ inverse transform block, and it operates as one $2n{\times}2n$ inverse transform block or two $n{\times}n$ inverse transform blocks. Thus, same number of pixels are processed in the same time, but it suffers from increased hardware size due to extra $n{\times}n$ inverse transform block. To avoid this problem, a novel $8{\times}8$ HEVC inverse core transform architecture was proposed to eliminate extra $4{\times}4$ inverse transform block based on multiplier reuse. This paper extends this approach and proposes a novel HEVC $16{\times}16$ inverse core transform architecture. Its frame processing time is same in $4{\times}4$, $8{\times}8$, and $16{\times}16$ inverse core transforms, and reduces gate counts by 13%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.4
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• pp.953-958
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• 2013

In this paper, an efficient hardware architecture is proposed for $32{\times}32$ inverse transform HEVC decoder. HEVC is a new image compression standard to deal with much larger image sizes compared with conventional image codecs, such as 4k, 8k images. To process huge image data effectively, it adopts various new block structures. Theses blocks consists of $4{\times}4$, $8{\times}8$, $16{\times}16$, and $32{\times}32$ block. This paper suggests an effective structures to process $32{\times}32$ inverse transform. This structure of inverse transform adopts the decomposed $16{\times}16$ matrixes of $32{\times}32$ matrix, and simplified the operations by implementing multiplying with shifters and adders. Additionally the operations frequency is downed by using multicycle paths. Also this structure can be easily adopted to a multi-size transform or a forward transform block in HEVC codec.

• Journal of IKEEE
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• v.17 no.4
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• pp.570-578
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• 2013

This paper proposed an $8{\times}8$ HEVC inverse core transform architecture reusing multipliers. In HEVC core transform, processing of lower size block is identical with even part of upper size block. So an $8{\times}8$ core transform architecture can process both $8{\times}8$ and $4{\times}4$ core transforms. However, when $8{\times}8$ core transform architecture is exploited, frame processing time doubles in $4{\times}4$ core transform, since $8{\times}8$ and $4{\times}4$ core transforms concurrently process 8 and 4 pixels, respectively. In this paper, a novel inverse core transform architecture is proposed based on multiplier reuse. It runs as an $8{\times}8$ inverse core transformer or two $4{\times}4$ inverse core transformer. Its frame processing time is same in $8{\times}8$ and $4{\times}4$ core transforms, and reduces gate counts by 12%.

• Journal of IKEEE
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• v.19 no.4
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• pp.596-602
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• 2015

In this paper, a unified inverse transformer is designed for HEVC and VP9. The proposed architecture performs all modes of HEVC and VP9 in the unified inverser transformer, such as $4{\times}4{\sim}32{\times}32$ HEVC IDCT, $4{\times}4$ HEVC IDST, $4{\times}4{\sim}32{\times}32$ VP9 IDCT, $4{\times}4{\sim}16{\times}16$ VP9 IADST and $4{\times}4$ IWHT. Same computations are used in HEVC IDCT and VP9 IDCT, except for the scales of the coefficients. Similarly, same computations are used in HEVC $4{\times}4$ IDST and VP9 $4{\times}4$ IADST, except for the scales of the coefficients. Furthermore, HEVC IDCT, VP9 IDCT, and VP9 IADST are the subsets of upper level IDCTs. The proposed architecture reuses multipliers when the computation is identical. Also it shares adders and butterfly structures even when the multiplier coefficients are different. So it reduces the hardware size significantly. Synthesized in 0.18 um technology, the gate count is 456,442 gates. which achieved 22.6% reduction compared to conventional architectures.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2253-2260
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• 2012

In this paper, an efficient hardware architecture is proposed for inverse transform and inverse quantization of H.264/AVC decoder. The previous inverse transform and quantization architecture has a different AC and DC coefficients decoding order. In the proposed architecture, IQ is achieved after IT regardless of the DC or AC coefficients. A common operation unit is also proposed to reduce the computational complexity of inverse quantization. Since division operation is included in the previous architecture, it will generate errors if the processing order is changed. In order to solve the problem, the division operation is achieved after IT to prevent errors in the proposed architecture. The architecture is implemented with 3-stage pipeline and a parallel vertical and horizontal IDCT is also implemented to reduce the operation cycle. As a result of analyzing the proposed ITIQ architecture operation cycle for one macroblock, the proposed one has improved by 45% than the previous one.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2006.06a
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• pp.277-278
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• 2006

This paper presents circuit models and control algorithms of distributed generation system(DGS) which consists of Z-type converter and PWM inverter Z-type converter which employs both the L and C passive components and shoot-through zero vectors instead of the conventional DC/DC converter in order to step up DC-link voltage. Discrete time sliding mode control with the asymptotic observer is used for current control.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.187-189
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• 2007

In this paper, we present a model-driven approach for RTOS-based embedded software development and an automated tool that produces RTOS-specific code or RTOS-independent code. We define generic RTOS APIs (Application Programming Interface) that are not bound to any specific RTOS but provide most of typical RTOS services. Generic RTOS APIs can be used to describe application's RTOS-related behavior, The proposed API translator translates task code between C-code for specific RTOS and intermediate code using generic API. Also, the result can be extended to other RTOS's modifying XML transformation rule.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5389-5396
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• 2012

In this paper, an optimized residual data decoder architecture is proposed to improve the performance in H.264/AVC. The proposed architecture is an integrated architecture that combined parallel inverse transform architecture and parallel inverse quantization architecture with common operation units applied new inverse quantization equations. The equations without division operation can reduce execution time and quantity of operation for inverse quantization process. The common operation unit uses multiplier and left shifter for the equations. The inverse quantization architecture with four common operation units can reduce execution cycle of inverse quantization to one cycle. The inverse transform architecture consists of eight inverse transform operation units. Therefore, the architecture can reduce the execution cycle of inverse transform to one cycle. Because inverse quantization operation and inverse transform operation are concurrency, the execution cycle of inverse transform and inverse quantization operation for one $4{\times}4$ block is one cycle. The proposed architecture is synthesized using Magnachip 0.18um CMOS technology. The gate count and the critical path delay of the architecture are 21.9k and 5.5ns, respectively. The throughput of the architecture can achieve 2.89Gpixels/sec at the maximum clock frequency of 181MHz. As the result of measuring the performance of the proposed architecture using the extracted data from JM 9.4, the execution cycle of the proposed architecture is about 88.5% less than that of the existing designs.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.314-315
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• 2008

본 논문에서는 임베디드 리눅스와 uCOS-2 간 소스코드 변환에 대한 연구를 위해 API 정변환/역변환기(API 변환기)를 이용하여 두 RTOS 간 소스코드 변환을 실험한다. API 변환기는 임베디드 소프트웨어의 개발을 돕기 위해 개발된 프로그램으로서, 정변환과 역변환 기능을 이용하여 이종 RTOS 간 소스코드를 자동으로 상호 변환한다. 정변환이란 중간형태의 C-코드인 CIC 파일에서 특정 RTOS를 위한 C-코드로 변환하는 것을 의미한다. 반대로 역변환은 특정 RTOS를 위한 C-코드로부터 CIC 파일로 변환하는 것을 가리킨다. 본 논문의 실험에서는 임베디드 리눅스와 uCOS-2의 동기화 소스코드 예제를 API 변환기를 이용하여 상호 변환해본다. 그리고 변환된 소스코드의 정상동작 여부를 확인하기 위해 각각의 타깃보드 위에 소스코드를 포팅한다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.12
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• pp.2247-2250
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• 2007

This paper presents an automated API translator for embedded software development based on a model-driven approach. Since MDA(Model Driven Architecture) provides little support for the development of embedded software, we propose a new approach containing its advantages. First, we define #generic APIs# which do not depend on any RTOS#s but provide most of typical RTOS services. We can describe RTOS-related behaviors of target application using these generic APIs in a CIC(Common Intermediate Code). Then, we propose a transformation tool for translating between a CIC using generic APIs and a C-code for specific RTOS. The proposed API translator converts them using XML transformation rule which is defined outside. It indicates that an API translator extends to other RTOS#s by modifying or adding the transformation rule. From the experiment. we validate the proposed method.