• Title/Summary/Keyword: 여분

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SRAM Reuse Design and Verification by Redundancy Memory (여분의 메모리를 이용한 SRAM 재사용 설계 및 검증)

  • Shim Eun sung;Chang Hoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.4A
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    • pp.328-335
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    • 2005
  • bIn this paper, built-in self-repair(BISR) is proposed for semiconductor memories. BISR is consisted of BIST(Buit-in self-test) and BIRU(Built-In Remapping Uint). BIST circuits are required not oがy to detect the presence of faults but also to specify their locations for repair. The memory rows are virtually divided into row blocks and reconfiguration is performed at the row block level instead of the traditional row level. According to the experimental result, we can verify algorithm for replacement of faulty cell.

A Study On The Reliability Characteristics of Fail-Safe Control Logic (고장-안전 제어논리의 신뢰성 특성에 관한 연구)

  • 한상섭;이정석;김민수;이기서
    • Proceedings of the Korean Reliability Society Conference
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    • 2000.04a
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    • pp.247-253
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    • 2000
  • 본 논문은 정보 여분(Information Redundancy)에서의 에러 검출 코딩(Error Detect Coding) 기법을 이용하여 3-out-of-6 자체 검사기를 설계하고, 주기적인 코드(Frequency Coding) 주입을 통해 고장-안전 제어 논리를 모델링 했다. 고장-안전 제어 논리 모듈과 TMR(Triple Modular Redundancy)의 단일 모듈간에 대해서 신뢰성 병렬 수치 해석을 수행하였고, 이때 고장-안전 제어 논리가 기존의 하드웨어 여분 기법보다 시스템 소모비용과 기능적 오버헤드가 감소되어 기능신뢰성이 증가되는 결과를 얻었다.

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디지털 고장포용 시스템의 개념 및 특성 - 컴퓨터 기술

  • 이대현;윤재영;김학배
    • 전기의세계
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    • v.46 no.9
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    • pp.15-22
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    • 1997
  • 본 논문은 고장포용 시스템에서 고려되는 결함, 오류 및 고장의 개념과 특성을 살펴보고, 고장에 대한 강인성을 부가하기 위한 공간 여분(spatial redundancy) 및 시간 여분(time redundandy)을 바탕으로 다양한 고장포용의 설계 기법을 설명하며, 또한 고장포용 시스템의 성능을 평가하기 위한 다양한 기준중 확률적 접근방식에 바탕을 둔 신뢰도(reliability)와 가용성(availability), 그리고 유지성(maintainability)에 대해 설명한다. 또한, 고장포용기법의 연구용 목적으로 개발되어 일부는 실제 활용되고 있는 대표적인 고장포용 시스템들인 FTMP[3], STAR[4], SIEF[5], C.vmp[6] 등에 대해서 간단히 살펴보도록 하겠다.

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Reliability Analysis of the Communications & Broadcasting Satellite Transponder and its Optimal Design (통신방송위성 중계기의 신뢰도 분석 및 최적 설계)

  • Kim, Young-Suk;Chang, Young-Keun;Jeong, Chul-Oh
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.30 no.8
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    • pp.94-102
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    • 2002
  • Since it would be almost impossible to recover and/or repair the satellite in space once it has been launched, a detailed analysis and design, manufacturing using the high quality workmanship, and qualification and acceptance tests in space-simulation environments are necessary for all satellite components prior to launch. Even though these efforts arc made, the failure can still occur. Therefore, redundancy should be considered in the satellite design for continuous operations in preparation for part or equipment failure. In this paper, the reliability analysis of the transponder, which is a payload of Communications & Broadcasting Satellite being developed by ETRI, was performed and compared for various design cases with different redundancies to find the optimal design. The optimal design has been finalized by investigating how the redundant components are composed from the viewpoint of technical performance measures, such as reliability, cost, schedule, and mass.

16×16 HEVC Inverse Core Transform Architecture Using Multiplier Reuse (곱셈기를 재사용하는 16×16 HEVC 코어 역변환기 설계)

  • Lee, Jong-Bae;Lee, Seongsoo
    • Journal of IKEEE
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    • v.19 no.3
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    • pp.378-384
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    • 2015
  • In conventional HEVC inverse core transform architectures, extra $n{\times}n$ inverse transform block is added to $2n{\times}2n$ inverse transform block, and it operates as one $2n{\times}2n$ inverse transform block or two $n{\times}n$ inverse transform blocks. Thus, same number of pixels are processed in the same time, but it suffers from increased hardware size due to extra $n{\times}n$ inverse transform block. To avoid this problem, a novel $8{\times}8$ HEVC inverse core transform architecture was proposed to eliminate extra $4{\times}4$ inverse transform block based on multiplier reuse. This paper extends this approach and proposes a novel HEVC $16{\times}16$ inverse core transform architecture. Its frame processing time is same in $4{\times}4$, $8{\times}8$, and $16{\times}16$ inverse core transforms, and reduces gate counts by 13%.

Research on the PAPR Reduction Method using Selection of Extra Code Set in PB/MC-CDMA System (PB/MC-CDMA 시스템에서 여분의 코드집합을 이용한 PAPR 감쇄기법에 관한 연구)

  • Lee, Kyu-Jin;Lee, Dong-Joon;Lee, Kye-San;Kim, Jin-Young
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.8 no.1
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    • pp.110-118
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    • 2009
  • The PB/MC-CDMA(Partial Block Multi Carrier Code Division Multilple Access) system can improve the performance by reducing the ICI(Inter-Code Interference) between users. Also, this system can achieve the frequency diversity gain by avoiding ISI(Inter Symbol Interference). Therefore, the performance of PB/MC-CDMA system is better than that of conventional MC-CDMA(Multi Carrier Code Division Multiple Access) system. However, similarly to other multi-carrier systems, it still has a PAPR(Peak to Average Power Ratio) issue. In this paper, we propose a peak power reduction technique involving optimized spreading code selection without side information for the PB/MC-CDMA. The PB/MC-CDMA system in each block of units reuses the code so the extra code will be remained. This extra code is divided into several groups to calculate the PAPR and solving the PAPR problem by transferring the selected code which has minimum peak power.

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A Design and Implementation of the Division/square-Root for a Redundant Floating Point Binary Number using High-Speed Quotient Selector (고속 지수 선택기를 이용한 여분 부동 소수점 이진수의 제산/스퀘어-루트 설계 및 구현)

  • 김종섭;조상복
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.37 no.5
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    • pp.7-16
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    • 2000
  • This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It performed the division and square-toot by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

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Efficient bit-parallel multiplier for GF(2$^m$) defined by irreducible all-one polynomials (기약인 all-one 다항식에 의해 정의된 GF(2$^m$)에서의 효율적인 비트-병렬 곱셈기)

  • Chang Ku-Young;Park Sun-Mi;Hong Do-Won
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.7 s.349
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    • pp.115-121
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    • 2006
  • The efficiency of the multiplier largely depends on the representation of finite filed elements such as normal basis, polynomial basis, dual basis, and redundant representation, and so on. In particular, the redundant representation is attractive since it can simply implement squaring and modular reduction. In this paper, we propose an efficient bit-parallel multiplier for GF(2m) defined by an irreducible all-one polynomial using a redundant representation. We modify the well-known multiplication method which was proposed by Karatsuba to improve the efficiency of the proposed bit-parallel multiplier. As a result, the proposed multiplier has a lower space complexity compared to the previously known multipliers using all-one polynomials. On the other hand, its time complexity is similar to the previously proposed ones.

Simulating Combustion Tests for the Verification of Baffle Gap of Optimal Damping Characteristics in Liquid Rocket Combustors (로켓연소기에서 최적의 감쇠특성을 보이는 분사기형 배플의 간극 검증을 위한 상압모사연소시험)

  • Kim, Hong-Jip;Lee, Kwang-Jin;Choi, Hwan-Seok
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.36 no.2
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    • pp.179-185
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    • 2008
  • Simulating combustion tests have been performed to elucidate the effect of baffle gaps on the optimal damping characteristics in liquid rocket combustors where coaxial injectors are installed. Amplitude of pressure oscillation in model combustion chamber and the combustion stability margin are used to quantify the damping capacitance of baffles. Satisfactory agreement has been achieved with the results of cold acoustic tests. Present results have shown that the optimal gap for high acoustic damping capacity has also the large combustion stability margin in simulating combustion tests. Therefore, the present results can be utilized to determine the baffle length and optimal gap in full-scaled rocket combustors.

Parametric Study on the Pressure Continuity Residual for the Stabilization of Pressure in Incompressible Materials (비압축성 물체의 압력해 안정화를 위한 압력연속여분치의 매개변수 연구)

  • 이상호;김상효
    • Computational Structural Engineering
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    • v.8 no.4
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    • pp.189-198
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    • 1995
  • The conventional finite element formulations for incompressible materials show pressure oscillations or pressure modes in four-node quadrilateral elements of commonly used displacement and pressure interpolations. The criterion for the stability in the pressure solution is the so-called Babugka-Brezzi stability condition, and the above elements do not satisfy this condition. In this study, a pressure continuity residual based on the pressure discontinuity at element interfaces is used to study the stabilization of pressure solutions in bilinear displacement-constant pressure four-node quadrilateral elements. This pressure residual is implemented in Q1P0 element derived from the conventional incompressible elasticity. The pressure solutions can be stable with the pressure residual though they exhibit sensitivity to the stabilization parameters. Parametric study for the solution stabilization is also discussed.

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