• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.5
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• pp.1061-1066
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• 2012

A digital memory has been widely used as a device for storing information due to its reliable, fast and relatively simple control circuit. However, the storage of the digital memory will be limited by the inablility to make smaller linewidths. One way to dramatically increase the storeage capability of the memory is to change the type of stored data from digital to analog. The analog memory fabricated in a standard single poly 0.6um CMOS process has been developed. Single cell and adjacent circuit block for programming have been designed and characterized. Applications include low-density non-volatile memory, control of redundancy in SRAM and DRAM memories, ID or security code registers, and image and sound memory.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.8
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• pp.1227-1234
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• 2013

An analog array with a 1.2 double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.30-37
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• 1998

An analog array with a 1.2 $\mu\textrm{m}$ double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.105-111
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• 2013

We have developed an analog associative memory implemented with an analog array which has linear writing and erasing characteristics. The associative memory adopts a winner-take-all strategy. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We also present a system architecture that enables highly-paralleled fast writing and quick readout as well as high integration density. A multiple memory cell configuration is also presented for achieving higher integration density, quick readout, and fast writing. The system technology presented here is ideal for a real time recognition system. We simulate the function of the mechanism by menas of Hspice with $1.2{\mu}$ double poly CMOS parameters of MOSIS fabrication process.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.3
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• pp.357-364
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• 2015

This research presents a DC-DC converter controller implemented with an analog memory. The structure of the converter will contribute to solve the stability problem unavoidable in a conventional closed loop converter. The analog memory will be used for realizing CAM(Contents Addressable Memory) which contains the output of the converter and the relevant duty ratio, respectively. The operation for reading in the memory is executed with an absolute differencing circuit and a WTA(Winner-Take-All) circuit suitable for a nearest-match function of the CAM. We also present a system architecture that enables highly-paralleled fast writing and quick readout as well as high integration density.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.4
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• pp.545-552
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• 2011

In this article, reference voltages in a general flash ADC are not obtained from a series of resistors but floating gates. When a behavior model simulation was performed in a pipelined ADC including the suggested flash ADC as a result of an ADC's overall function, it showed results that SNR is approximately 77 dB and resolution is 12 bit. And more than almost 90% showed INL within ${\pm}0.5$ LSB, and like INL, more than 90% showed DNL within ${\pm}0.5$ LSB.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.495-496
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• 2008

본 논문에서는 UHF 대역 RFID 의 국제표준인 ISO/IEC 18000-6C 표준을 만족하는 태그 칩을 위한 저전력 고성능 아날로그 회로를 설계하였다. 설계된 아날로그 회로는 성능 테스트를 위해 메모리 블록을 포함하고 있으며, 태그의 인식률과 경제성을 위해 저 전력 및 칩 면적의 최소화에 중점을 두고 설계하였다. 설계된 UHF 대역 RFID 태그용 아날로그 회로는 0.24Vpeak의 RF 입력으로 동작이 가능하며, 칩 면적은 $552.5{\mu}m{\times}338.8{\mu}m$, UHF 대역 RFID 태그 칩에 적합한 작은 면적을 갖는다.

• Journal of Advanced Navigation Technology
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• v.23 no.5
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• pp.452-459
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• 2019

In this paper, we describe a PCM encoder structure that can update the telemetry system parameters in real time. In the PCM encoder, an analog signal control unit for FPGA, flash memory, and sensor data acquisition was constructed. UART communication, analog signal control, flash memory control, and frame generation are possible through logic inside FPGA of PCM encoder. UART communication allows the PC to transmit parameter data to the PCM encoder, and flash memory is controlled to update the parameter of the telemetry system in real time and finally the frame is formed. Simulation and verification were performed to confirm whether the parameter data is updated in real time, and the proposed structure was used to construct a telemetry system with enhanced flexibility and convenience.

• Journal of Biomedical Engineering Research
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• v.19 no.3
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• pp.251-260
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• 1998

The Holter monitoring system is a widely used noninvasive diagnostic tool for ambulatory patient who may be at risk from latent life-threatening cardiac abnormalities. In this paper, we design a high performance intelligent holter monitoring system which is characterized by the small-sized and the low-power consumption. The system hardware consists of one-chip microcontroller(68HC11E9), ECG preprocessing circuit, and flash memory card. ECG preprocessing circuit is made of ECG preamplifier with gain of 250, 500 and 1000, the bandpass filter with bandwidth of 0.05-100Hz, the auto-balancing circuit and the saturation-calibrating circuit to eliminate baseline wandering, ECG signal sampled at 240 samples/sec is converted to the digital signal. We use a linear recursive filter and preprocessing algorithm to detect the ECG parameters which are QRS complex, and Q-R-T points, ST-level, HR, QT interval. The long-term acquired ECG signals and diagnostic parameters are compressed by the MFan(Modified Fan) and the delta modulation method. To easily interface with the PC based analyzer program which is operated in DOS and Windows, the compressed data, that are compatible to FFS(flash file system) format, are stored at the flash memory card with SBF(symmetric block format).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.3
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• pp.197-203
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• 1986

The images which are scanned by CCTV are converted to digital signal and 6502 Microcomputer processes data by Transform coding. Thus data is reduced to $64{ imes}64$pixels and input by outer memory using same address with inner one for the fast process. Hadmard Transform, Weighted Hadamard Transform which is weighted in the center of matrix and Haar Transform are programmed by assembly language and every Transform is dome within one second.