• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.1-8
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• 1998

This paper presents an asynchronous DS/CDMA multiuser detector, which is a two stage, symbol-by-symbol scheme consisting of conventional detectors followed by linear decorrelating detectors. The conventional detector first makes temporal decisions and the detected symbols are delayed by one symbol period to be used for the selection of decorrelating bases in the subsequent decorrelaing detection stage. It also employs a bank of early-late correlators in place of a bank of single correlators taking the small offset of chip timing asynchronism into account. The proposed detector requires only the coarse knowledge of relative time delays of interfering users and is suitable for digital implementation. To verify the detector performance, the analytical BER performance will be given and compared with the simulation results for BPSK DS/CDMA signals in AWGN channel. While the performance of the proposed detector will be analyzed for time-limited signal, the simulation is carried out for both the time-limited and band-limited signals. As can be seen in the simulation results, the proposed scheme shows good results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.41-50
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• 2010

In this paper, an area-efficient symbol detector is proposed for MIMO communication systems with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode for MIMO transmission technique, and shows the optimal maximum likelihood (ML) performance. Also, by sharing the hardware block with multi-stage pipeline structure and using the complex multiplier based on polar-coordinate，the complexity of the proposed architecture is dramatically decreased. The proposed symbol detector was designed in hardware description language (HDL) and implemented with Xilinx Virtex-5 FPGA. With the proposed architecture, the number of logic slices for the proposed symbol detection is 52490 and the number of DSP48s (dedicated multiplier) is 52, which are reduced by 35.3% and 85.3%, respectively, compared with the conventional architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.7
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• pp.545-551
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• 2013

Timing recovery loop composed of the Timing Error Detector(TED), loop filter and resampler is widely used for the timing synchronization in MQASK receivers. Since TED is sensitive to the delay between the symbol period of the signal and sampling period, the output is averaged out when the symbol rate and sampling rate are quite different the recovery loop cannot work at all. This paper presents a sampling frequency discriminator (SRD), which detects the frequency offset of the sampling clock to the symbol clock of the MQASK data transmitted. Employing the SRD, the closed loop timing recovery scheme performs the frequency-aided timing acquisition and achieve the synchronization at extremely high sampling frequency offset, which can be used in variable symbol rate MQASK receivers.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.7
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• pp.9-15
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• 1999

In this paper, we propose a bit synchronizer which is suitable for frequency hopping systems. The proposed bit synchronizer is an ADPLL in which the digital loop filter is combined with an error symbol detecting circuit. Suppressing the tracking process, when hop mute and impulse noises are detected, improves the performance of the digital loop filter and enhances the probability of the frequency hopping system. Simulation results demonstrate an improved performance of the proposed bit synchronizer compared with existing ones.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.16 no.2
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• pp.153-160
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• 2017

Recently, the demand has continued to increase for higher data rates and improved multimedia services through wireless internet access. In order to increase the data rate and link reliability, 3GPP LTE/A and IEEE 802.16e/m WiMAX systems incorporate MIMO transmission schemes. Since the hardware complexity increases with the number of transmit data streams and mobile devices have limited physical dimensions, an multiple input multiple output (MIMO) ystem with two antennas at both the transmitter and the receiver ($2{\times}2$) is considered to be a possible solution for mobile devices. In this paper, a low-complexity soft output MIMO symbol detector based on Modified-SQRD is proposed for mobile devices with two transmit and two receive antennas.

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.220-226
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• 2010

In this paper, an low power symbol detector is proposed for MIMO communication system with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing (SM) mode and spatial diversity (SD) mode for MIMO transmission technique, and shows the optimal maximum likelihood (ML) performance. Also, by sharing the hardware block and using the dedicated clock MIMO modes, the power of the proposed architecture is dramatically decreased. The proposed symbol detector was designed in hardware description language (HDL) and synthesized to logic gates using a $0.13-{\mu}m$ CMOS standard cell library. The power consumption was estimated by using Synopsys Power CompilerTM, which is reduced by maximum 85%, compared with the conventional architecture.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.9-14
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• 2013

In this paper, we propose a low complexity bilateral search SIC for OFDM in fast time-varying channels. Due to the possibility of error propagation in SIC, symbol detection ordering within the block of symbols has a significant effect on the overall performance. In this paper, the first symbol to be detected is determined based on CSEP values, and then the next symbol to be detected is selected according to the updated CSEP while bilaterally searching from the boundary of the detected symbol group. Through computer simulations, we show that the proposed method has performance improvements with almost the same computation complexity over the conventional methods in the high SNR region. It has a performance approaching the MFB, known as the performance upper bound, within 2dB at the BER of $10^{-5}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.74-86
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• 2002

This paper proposes a VLSI architecture for high-speed data processing of the differential phase detectors with the decision feedback. To improve the BER performance of the conventional differential phase detection, DF-DPD, DPD-RGPR and DFDPD-SA have been proposed. These detection methods have the architecture feedbacking the detected phase to reduce the noise of the previous symbol as phase reference. However, the feedback of the detected phase results in lower data processing speed than that of the conventional differential phase detection. In this paper, the VLSI architecture was proposed for high-speed data processing of the differential phase detectors with decision feedback. The Proposed architecture has the pre-calculation method to previously calculate the results on 'N'th step at 'M-1'th step and the pre-decision feedback method to previously feedback the predicted phases at 'M-1'th step. The architecture proposed in this paper was implemented to RTL using VHDL. The simulation results show that the Proposed architecture obtains the high-speed data processing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.11B
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• pp.1879-1883
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• 2000

디지털 자기 기록 저장기기에서 채널 밀도가 증가하면 심각한 인접심볼 간섭과 비선형 왜곡이 야기된다. 본 논문에서는 심각한 비선형 인접심볼 간섭과 비선형 왜곡을 극복하기 위한 방법으로 기존의 등화기 대신 NLTE(neural linear transversal equalizer)를 등화기로 사용하고 검출기로는 터보 코드를 사용한 NLTE/TC 구조를 제안한다. 채널 밀도 S=2.5에서 부분 삭제가 0.7 정도 존재할 때, 코드율이 8/9일 때는 $10^{-5}$의 비트 에러율을 18dB 이후에서 만족하며, 코드율이 16/17일 때는 20dB 이후에서 만족함을 알 수 있었다. 채널 밀도 S=3에서 부분 삭제가 0.6 정도 존재할 때 코드율이 8/9일 때는 $10^{-5}$의 비트 에러율을 22dB 이후에서 만족하고, 코드율이 16/17일 때는 24dB 이후에서 만족함을 확인할 수 있었다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2006.11a
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• pp.197-200
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• 2006

ATSC DTV시스템에서는 심볼타이밍 동기를 위해서 ATSC규격에 소개되어있는 $77.3{mu}s$ 마다 반복적으로 삽입되어있는 세그먼트 싱크를 이용하는 세그먼트 동기 방법 또는 QAM과 같은 다중레벨을 가지는 신호에 일반적으로 사용되는 가드너(Gardner)방법을 사용한다. 이중 가드너 방법은 매심볼마다 타이밍 에러성분을 추출하므로 다중경로 채널에서 타이밍동기를 추적하면서 유지하는데 유리한 방식이어서 일반적으로 사용한다. 가드너 방법을 이용하는 ATSC DTV시스템에서 가드너 방법에 에러를 검출하기 위해 사용되는 가드너 타이밍 에러 검출기(Timing Error Detector)는 수신단의 파워레벨이 기준 파워레벨에서 크게 벗어날 경우 에러를 검출 할 수 없는 문제점을 가지고 있다. 이를 해결 하기 위해 가드너 타이밍 에러 검출기 블록 앞에 송신파워 레벨과 수신파워 레벨의 비를 이용하여 정상적인 수신 파워 레벨로 수신학 수 있도록 보정하는 블록을 추가하여 전체적인 동기성능을 향상시키는 알고리즘을 제안한다.