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A Study on the Application of Bushings Fire Prevent Structure to Prevent Fire Spread of Transformer (변압기의 화재확산 방지를 위한 부싱 방화구조체 적용에 관한 연구)

  • Kim, Do-Hyun;Cho, Nam-Wook;Yoon, Choung-Ho;Park, Pil-Yong;Park, Keun-Sung
    • Fire Science and Engineering
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    • v.31 no.5
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    • pp.53-62
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    • 2017
  • Electric power which is the energy source of economy and industries requires long distance transportation due to regional difference between its production and consumption, and it is supplied through the multi-loop transmission and distribution system. Prior to its actual use, electric power flows through several transformations by voltage transformers in substations depending on the characteristics of each usage, and a transformer has the structure consisting of the main body, winding wire, insulating oil and bushings. A transformer fire that breaks out in substations entails the primary damage that interrupts the power supply to houses and commercial facilities and causes various safety accidents as well as the secondary economic losses. It is considered that causes of such fire include the leak of insulating oil resulting from the destruction of bottom part of bushings, and the chain reaction of fire due to insulating oil that reaches its ignition point within 1 second. The smoke detector and automatic fire extinguishing system are established in order to minimize fire damage, but a difficulty in securing golden time for extinguishing fire due to delay in the operation of detector and release of gas from the extinguishing system has become a problem. Accordingly, this study was carried out according to needs of active mechanism to prevent the spread of fire and block the leak of insulating oil, in accordance with the importance of securing golden time in extinguishing a fire in its early stage. A bushings fireproof structure was developed by applying the high temperature shape retention materials, which are expanded by flame, and mechanical flame cutoff devices. The bushings fireproof structure was installed on the transformer model produced by applying the actual standards of bushings and flange, and the full scale fire test was carried out. It was confirmed that the bushings fireproof structure operated at accurate position and height within 3 seconds from the flame initiation. It is considered that it could block the spread of flame effectively in the event of actual transformer fire.

An Energy Efficient Cluster Management Method based on Autonomous Learning in a Server Cluster Environment (서버 클러스터 환경에서 자율학습기반의 에너지 효율적인 클러스터 관리 기법)

  • Cho, Sungchul;Kwak, Hukeun;Chung, Kyusik
    • KIPS Transactions on Computer and Communication Systems
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    • v.4 no.6
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    • pp.185-196
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    • 2015
  • Energy aware server clusters aim to reduce power consumption at maximum while keeping QoS(Quality of Service) compared to energy non-aware server clusters. They adjust the power mode of each server in a fixed or variable time interval to let only the minimum number of servers needed to handle current user requests ON. Previous studies on energy aware server cluster put efforts to reduce power consumption further or to keep QoS, but they do not consider energy efficiency well. In this paper, we propose an energy efficient cluster management based on autonomous learning for energy aware server clusters. Using parameters optimized through autonomous learning, our method adjusts server power mode to achieve maximum performance with respect to power consumption. Our method repeats the following procedure for adjusting the power modes of servers. Firstly, according to the current load and traffic pattern, it classifies current workload pattern type in a predetermined way. Secondly, it searches learning table to check whether learning has been performed for the classified workload pattern type in the past. If yes, it uses the already-stored parameters. Otherwise, it performs learning for the classified workload pattern type to find the best parameters in terms of energy efficiency and stores the optimized parameters. Thirdly, it adjusts server power mode with the parameters. We implemented the proposed method and performed experiments with a cluster of 16 servers using three different kinds of load patterns. Experimental results show that the proposed method is better than the existing methods in terms of energy efficiency: the numbers of good response per unit power consumed in the proposed method are 99.8%, 107.5% and 141.8% of those in the existing static method, 102.0%, 107.0% and 106.8% of those in the existing prediction method for banking load pattern, real load pattern, and virtual load pattern, respectively.

Analysis of Seed Hair Formation Related Genes by EST Profiling in Carrot (Daucus carota var. sativa) (EST profiling을 통한 당근(Daucus carota var. sativa)의 종모 형성에 관련된 유전자 분석)

  • Hwang, Eun-Mi;Oh, Gyu-Dong;Shim, Eun-Jo;Jeon, Sang-Jin;Park, Young-Doo
    • Horticultural Science & Technology
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    • v.28 no.6
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    • pp.1039-1050
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    • 2010
  • Carrot is one of the useful crops used abundantly in cooking in Western as well as Asia regions such as China and Korea. However, seed coats have hairs which should be removed to increase germination rate. Furthermore, because of seed hairs, farmers face several additional losses, such as time consumption, manpower, capital and so on, for seed handling. To prevent these problems, study of gene related hair formation using short-hair seed lines is required. We analyzed genes related to hair formation from seed through expressed sequenced tag (EST) profiling, based on the fact that the development of carrot seed hair is related to cellulose synthesis pathway in secondary cell wall synthesis stage. To study the gene expression related to hair formation of the carrot seed, a cDNA library was constructed by using the early maturation stage of the short-hair line (659-1) and hairy seed line (677-14). In short-hair (659-1) and hairy seed (677-14) lines, results from of EST profiling through BLASTX search analysis using the NCBI database showed that 172 and 224 unigenes had significant homology with known protein sequences, whereas 233 and 192 unigenes were not, respectively. All ESTs were grouped into 16 categories according to their putative functions. Twenty nine unigenes among all ESTs were considered to be genes regulating seed hair development from cellulose synthesis pathway during secondary cell wall synthesis stage; in results, 14 unigenes related to seed hair development were found only in hairy seed line.

Sustainable Design Method of Reinforced Concrete Beam Using Embodied Energy Optimization Technique (내재에너지 최적화를 통한 철근 콘크리트 보의 지속가능 설계법)

  • Yoon, Young-Cheol;Kim, Kyeong-Hwan;Yeo, DongHun;Lee, Sang-Ho
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.34 no.4
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    • pp.1053-1063
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    • 2014
  • This study presents a sustainable design method that optimizes the embodied energy of concrete beam based on the concept of sustainable development that effectively utilizes natural resource and energy within the range that our succeeding generation can afford to utilize. In order to get the flexural strength carrying the ultimate load, concrete beam sections are designed by optimization that consists of the embodied energy as a objective function and the requirements of design code as constrained conditions. The sustainable design can be used to minimize the embodied energy consumed in material production, construction, operation, demolition of the infrastructure. As a result of comparison of the cost and the embodied energy optimizations based on practical beam sections, it is shown that 20% embodied energy saving and 35% $CO_2$ emission saving are achieved by sacrificing 10% cost increase. The sustainable design method provides a new effective methodology that manages the strength design concept based on cost minimization together with economic feasibility and sustainability. In addition, the method is expected to be applied to more various structural design practices.

Design of an 1.8V 6-bit 2GSPS CMOS ADC with an One-Zero Detecting Encoder and Buffered Reference (One-Zero 감지기와 버퍼드 기준 저항열을 가진 1.8V 6-bit 2GSPS CMOS ADC 설계)

  • Park Yu Jin;Hwang Sang Hoon;Song Min Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.6 s.336
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    • pp.1-8
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    • 2005
  • In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation, we present an Interpolation type architecture. In order to overcome the problems of high speed operation, a novel One-zero Detecting Encoder, a circuit to reduce the Reference Fluctuation, an Averaging Resistor and a Track & Hold, a novel Buffered Reference for the improved SNR are proposed. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply and occupies chip area of 977um $\times$ 1040um. Experimental result show that SNDR is 36.25 dB when sampling frequency is 2GHz and INL/DNL is $\pm$0.5LSB at static performance.

A Study on Characteristics of Eco-friendly Behaviors using Big Data: Focusing on the Customer Sales Data of Green Card (빅 데이터를 활용한 친환경행동 특성에 관한 연구: 대용량 그린카드 거래데이터를 중심으로)

  • Lim, Mi Sun;Kim, Jinhwa;Byeon, Hyeonsu
    • Journal of Digital Convergence
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    • v.14 no.1
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    • pp.151-161
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    • 2016
  • As part of a policy to address climate change and pollution problem, the government introduced a green credit card scheme in order to motivate pro-environmental behaviors in July 2011. It is important to present the specific ways to facilitate pro-environmental behaviors using the consumer behavior pattern data. This study was a result of data from total fifty seven thousands customer purchasing history data of green credit card to be created for the 3 months from January to March 2015. As the analysis process is put in to operation the analysis of the purchasing customer's profile firstly, and the second come into association analysis to consider the buying associations for green products purchasing networks, the third estimate the useful parameters to affect the customer's pro-environmental behavior and customer characteristics. It shows that royal customers are from 30 to 40 years old and their incomes are from 30 million won to 40 million won. Especially, they live in Daegu, Gyeonggi, and Seoul.

An Automation of CAD Tool License Sharing Scheme Within a Design Working Group (디자인 워킹 그룹을 위한 CAD 툴 라이센스 공유 기법의 자동화)

  • Jung Sung-Heon;Jhang Kyoung-Son;Yim In-Sung
    • Journal of KIISE:Computing Practices and Letters
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    • v.12 no.1
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    • pp.1-8
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    • 2006
  • Since most CAD tool companies are carrying out very expensive license policies, designers are sharing CAD tools with a limited number of licenses within a design working or research group. It is important to share and use them efficiently, because CAD tool licenses are very valuable resources. Designers should know CAD tool license information such as available number of licenses, types, and configuration methods to use CAD tools properly in their group. Usually, this information is provided by managers who administrate CAD tool license servers in the specific design group. In the previous CAD tool licenses sharing methods, designers have to get CAD tool license information manually and setup the environments with their own hands, If a new designer comes into the design working group, the designer wastes unnecessary time and effort due to these manual processes. As a result, designer's productivity and utilization of CAD tools will decrease. Besides, managers also waste their time and effort, since they should provide CAD tool license information manually to each desiEner. In this paper, we present a more efficient scheme to share CAD tool licenses based on directory service. The proposed method automates not only the communication processes between managers and designers, but also the license configuration steps. We expect this scheme will reduce time and effort of designers and managers as well as enhance the utilization of CAD tools.

A Radio-Frequency PLL Using a High-Speed VCO with an Improved Negative Skewed Delay Scheme (향상된 부 스큐 고속 VCO를 이용한 초고주파 PLL)

  • Kim, Sung-Ha;Kim, Sam-Dong;Hwang, In-Seok
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.42 no.6
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    • pp.23-36
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    • 2005
  • PLLs have been widely used for many applications including communication systems. This paper presents a VCO with an improved negative skewed delay scheme and a PLL using this VCO. The proposed VCO and PLL are intended for replacing traditional LC oscillators and PLLs used in communication systems and other applications. The circuit designs of the VCO and PLL are based on 0.18um CMOS technology with 1.8V supply voltage. The proposed VCO employs subfeedback loops using pass-transistors and needs two opposite control voltages for the pass transistors. The subfeedback loops speed up oscillation depending on the control voltages and thus provide a high oscillation frequency. The two voltage controls have opposite frequency gain characteristics and result in low phase-noise. The 7-stage VCO in 0.18um CMOS technology operates from $3.2GHz\~6.3GHz$ with phase noise of about -128.8 dBc/Hz at 1MHz frequency onset. For 1.8V supply voltage, the current consumption is about 3.8mA. The proposed PLL has dual loop-filters for the proposed VCO. The PLL is operated at 5GHz with 1.8V supply voltage. These results indicate that the proposed VCO can be used for radio frequency operations replacing LC oscillators. The circuits have been designed and simulated using 0.18um TSMC library.

Design of an 1.8V 8-bit 500MSPS Cascaded-Folding Cascaded-Interpolation CMOS A/D Converter (1.8V 8-bit 500MSPS Cascaded-Folding Cascaded-Interpolation CMOS A/D 변환기의 설계)

  • Jung Seung-Hwi;Park Jae-Kyu;Hwang Sang-Hoon;Song Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.5 s.347
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    • pp.1-10
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    • 2006
  • In this paper, an 1.8V 8-bit 500MSPS CMOS A/D Converter is proposed. In order to obtain the resolution of 8bits and high-speed operation, a Cascaded-Folding Cascaded-Interpolation type architecture is chosen. For the purpose of improving SNR, Cascaded-folding Cascaded-interpolation technique, distributed track and hold are included [1]. A novel folding circuit, a novel Digital Encoder, a circuit to reduce the Reference Fluctuation are proposed. The chip has been fabricated with a $0.18{\mu}m$ 1-poly 5-metal n-well CMOS technology. The effective chip area is $1050{\mu}m{\times}820{\mu}m$ and it dissipates about 146mW at 1.8V power supply. The INL and DNL are within ${\pm}1LSB$, respectively. The SNDR is about 43.72dB at 500MHz sampling frequency.

A DC Reference Fluctuation Reduction Circuit for High-Speed CMOS A/D Converter (고속 CMOS A/D 변환기를 위한 기준전압 흔들림 감쇄 회로)

  • Park Sang-Kyu;Hwang Sang-Hoon;Song Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.6 s.348
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    • pp.53-61
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    • 2006
  • In high speed flash type or pipelining type A/D Converter, the faster sampling frequency is, the more the effect of DC reference fluctuation is increased by clock feed-through and kick-back. When we measure A/D Converter, further, external noise increases reference voltage fluctuation. Thus reference fluctuation reduction circuit must be needed in high speed A/D converter. Conventional circuit simply uses capacitor but layout area is large and it's not efficient. In this paper, a reference fluctuation reduction circuit using transmission gate is proposed. In order to verify the proposed technique, we designed and manufactured 6bit 2GSPS CMOS A/D converter. The A/D converter is based on 0.18um 1-poly 5-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies chip area of $977um\times1040um$. Experimental result shows that SNDR is 36.25 dB and INL/DNL ${\pm}0.5LSB$ when sampling frequency is 2GHz.