• Title/Summary/Keyword: 신뢰 전파 복호

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New Stopping Criteria for Iterative Decoding of LDPC Codes in H-ARQ Systems (H-ARQ 시스템에서 LDPC 부호의 반복 복호 중단 기법)

  • Shin, Beom-Kyu;Kim, Sang-Hyo;No, Jong-Seon;Shin, Dong-Joon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.9C
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    • pp.683-690
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    • 2008
  • By using inherent stopping criteria of LDPC codes, the average number of iterations can be substantially reduced at high signal to noise ratio (SNR). However, we encounter a problem when hybrid automatic repeat request (H-ARQ) systems are applied. Frequent failures of decoding at low SNR region imply that the decoder leaches the maximum number of iterations frequently and thus the decoding complexity increases. In this paper, we propose a combination of stopping criteria using the syndrome weight of tentative codeword. By numerical analysis, it is shown that the decoding complexity of given H-ARQ system is reduced by 70-80% with the proposed algorithms.

Improved Performance Decoding for LDPC Codes with a Large Number of Short Cycles (다수의 짧은 주기를 가진 LDPC 부호를 위한 향상된 신뢰 전파 복호)

  • Chung, Kyu-Hyuk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.2C
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    • pp.173-177
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    • 2008
  • In this paper, we improve performance of Low Density Parity Check (LDPC) codes with adding a large number of short cycles. Short cycles, especially cycles of length 4, degrade performance of LDPC codes if the standard BP (Belief Propagation) decoding is used. Therefore current researches have focused on removing cycles of length 4 for designing good performance LDPC codes. We found that a large number of cycles of length 4 improve performance of LDPC codes if a modified BP decoding is used. We present the modified BP decoding algorithm for LDPC codes with a large number of short cycles. We show that the modified BP decoding performance of LDPC codes with a large number of short cycles is better than the standard BP decoding performance of LDPC codes designed by avoiding short cycles.

Combined Normalized and Offset Min-Sum Algorithm for Low-Density Parity-Check Codes (LDPC 부호의 복호를 위한 정규화와 오프셋이 조합된 최소-합 알고리즘)

  • Lee, Hee-ran;Yun, In-Woo;Kim, Joon Tae
    • Journal of Broadcast Engineering
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    • v.25 no.1
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    • pp.36-47
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    • 2020
  • The improved belief-propagation-based algorithms, such as normalized min-sum algorithm (NMSA) or offset min-sum algorithm (OMSA), are widely used to decode LDPC(Low-Density Parity-Check) codes because they are less computationally complex and work well even at low SNR(Signal-to-Noise Ratio). However, these algorithms work well only when an appropriate normalization factor or offset value is used. A new method that uses a CMD(Check Node Message Distribution) chart and least-square method, which has been recently proposed, has advantages on computational complexity over other approaches to get optimal coefficients. Furthermore, this method can be used to derive coefficients for each iteration. In this paper, we apply this method and propose an algorithm to derive a combination of normalization factor and offset value for a combined normalized and offset min-sum algorithm to further improve the decoding of LDPC codes. Simulations on the next-generation broadcasting standards, ATSC 3.0 LDPC codes, prove that a combined normalized and offset min-sum algorithm which takes the proposed coefficients as correction coefficients shows the best BER performance among other decoding algorithms.

Implementation of an indoor wireless modem using direct sequence spectrum technology (직접시퀀스 대역 확산 방식을 이용한 실내 무선 모뎀의 구현)

  • 박병훈;김호준;황금찬
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.9A
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    • pp.2141-2152
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    • 1998
  • In this paper, we design and implement an indoor wireless modem using small signal of ISM band regulation, which can tranceive reliable data streams. We use direct sequence spead spectrum (DS-SS) signaling with synchronous BPSK and QPSK modulation, convolutional coding with viterbi decoding. The radio frequency module uses frequency devision duplexing in 900 MHz band, and the digital module is implemented with FPGAs for the purpose fo ASIC design. The perfomrance of our own acquistion and tracking circuit consisting digital matched filter and decision logic is proved by experiments, and the possibility of file transfer at indoor environment with the entrie system that the modem is connected the PC through RS-232C port is verified.

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