• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.3
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• pp.2-9
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• 2016

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.2
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• pp.162-168
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• 2005

In this paper, a digital current mode control is designed for the power converter applications. The designed digital current mode controller is derived analytically from the continuous time small signal model of the power converters. Due to the small signal model based derivations of the control law, the designed control method can be applicable to boost, buck, and buck-boost converters. It is also proven that the controlled power converter employing the designed digital current mode controller is always stable regardless of an operating conditions. In order to show the usefulness of a designed controller, experiments are carried out using a 16bit DSP micro-processor, TMS320LF2406A.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2049-2051
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• 2003

본 논문에서는 불확실성을 포함할지도 모르는 비선형 시스템의 추적 제어에 효과적인 퍼지모델기반 제어기에 대한 지능형 디지털 재설계 기법을 제안한다. TS 퍼지모델은 불확실 비선형 시스템의 퍼지모델링에 적용되었다. 안정화와 추적을 위한 퍼지모델기반 제어기를 설계하기 위해 확장 병렬 분산 보상 기법이 이용되었다. 설계된 연속시간 제어기는 지능형 디지털 재설계 기법을 이용해 등가의 이산시간 제어기로 변환되었다. 본 논문에서 제안한 지능형 디지털 재설계방법은 전형적인 단일 링크 유연 로봇 시스템에 적용하여 그 응용 가능성과 효용성을 입증한다.

• Journal of IKEEE
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• v.27 no.3
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• pp.234-238
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• 2023

In this paper, we propose a time-to-digital converter (TDC) with compensation capability for PVT (process, voltage, and temperature) variations. A typical delay line-based TDC measures time based on the inverter's propagation delay, making it fundamentally sensitive to PVT variations. This paper presents a method to minimize the resolution change of TDC by compensating for the propagation delay caused by the PVT variations. Additionally, it dopts Cyclic Vernier TDC (CVTDC) structure to provide a wide input detection range. The proposed CVTDC with PVT compensation function is designed using a 45nm CMOS process, consumes 8mW of power, offers a TDC resolution of 5 ps, and has an input detection range of about 5.1 ns.

• Proceedings of the Korea Society for Simulation Conference
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• 2000.04a
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• pp.180-185
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• 2000

발전소 등의 대규모 공정 플랜트에서 사용하고 있는 대부분의 상용 제어기는 PID 제어기이며, 온도 루프를 제외한 대부분의 제어루프가 PI 제어기를 채용하고 있다. 제어 시스템의 성능이 제어기 파라미터의 값에 의해 결정되므로, PI 제어기의 튜닝이 중요하다. 한편, 실제 현장에서의 PI 제어기의 튜닝은 많은 시간과 노력을 필요로 하는 시행착오에 의해서 이루어지고 있으며, 각 제어 루프 제어기 파라미터의 초기값 설정에 어려움을 갖고 있는 실정이다. PI 튜닝 기법이 많이 나와 있지만 시험 신호의 인가 문제로 인해 현장 활용에는 많은 어려움을 가지고 있다. 본 논문에서는 단순한 시험 신호로부터 PI 초기 설정값을 산출할 수 있는 방법에 대해서 알아본다. 또한 발전소에 적용된 국산 분산 제어 시스템을 보면, 대부분 데이터 로깅 시스템으로서만 활용되고 있고, 제어 시스템으로의 활용은 거의 이루어지지 않고 있으며, PID제어기에 대한 구현도 완벽하지 못하여 디지털 PI 제어기의구현 방법에 대한 고찰도 요구되고 있다. 본 논문에서는 디지탈 PI 제어기를 구현하는데 있어서 필요한 사항들, 즉 아날로그 제어기의 디지털 등가 제어기로의 변환 기법, 샘플링 주기의 결정 방법, 그리고 그 외에 공정 제어기가 가져야할 기능들에 대해서 언급한다. 그리고나서 PI 튜닝 기법과 아날로그 제어기의 디지털 등가 제어기로의 변환기법, 샘플링 주기 결정 방법 등에 대해 플랜트 모델을 선정하고 시뮬레이션을 통해 그 효용성을 보인다.

• Journal of IKEEE
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• v.16 no.1
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• pp.28-33
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• 2012

Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.

• Journal of IKEEE
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• v.24 no.4
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• pp.1058-1063
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• 2020

This paper proposes a 12-bit SAR A/D(Successive Approximation Register Analog-to-Digital) converter that operates at low power for bio-signal and sensor signal processing. The conventional SAR A/D converter utilized the reduction of the dynamic current, which resulted in reducing total power consumption. In order to solve the limitation of the sampling time due to charging/discharging of the capacitor for reducing dynamic current, the different sampling time on the C-DAC bit switch operation was applied to reduce the dynamic current. In addition, lowering the supply voltage of the digital block to 0.6V led to 70% reduction of the total power consumption of the proposed ADC. The proposed SAR A/D was implemented with CMOS 65nm process 1-poly 6-metal, operates with a supply voltage of 1.2V. The simulation results demonstrate that ENOB, DNL/INL, power consumption and FoM are 10.4 bits, ±0.5LSB./±1.2LSB, 31.2uW and 2.8fJ/step, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.87-93
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• 2010

This paper presents a high resolution, wide input range 2-step time-to-digital converter used in digital PLL. TDC is used to compare the DPLL output frequency with reference frequency and should be implemented with high resolution to improve the phase noise of DPLL. The conventional TDC consists of delay line realized inverters, whose resolution is determined by delay time of inverter and transistor size, resulting in limited resolution. In this paper, 2-step TDC with phase-interpolation and Time Amplifier is proposed to meet the high resolution and wide input range by implement the delay time less than an inverter delay. The gain of Time Amplifier is improved by using the delay time difference between two inverters. It is implemented in $0.13{\mu}m$ CMOS process and the die area is $800{\mu}m{\times}850{\mu}m$ Current consumption is 12 mA at the supply voltage of 1.2 V. The resolution and input range of the proposed TDC are 0.357 ps and 200 ps, respectively.

• The Journal of Information Technology
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• v.4 no.4
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• pp.51-63
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• 2001

Residue Number System has carry free operation and parallelism each modulus, So it is used for special purpose processor such as Digital Signal Processing and Neuron Processor. Magnitude comparison and sign detection are in need of Mixed Radix Conversion, and these operations are impediment to improve the operation speed. So in this Paper, MRC(Mixed Radix Converter) is designed using modified partitioned residue to speed up the operation of MRC, so it has progressed maximum twice operation time but increased the size of converter comparison to other converter.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.1
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• pp.27-36
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• 1983

The 12-Channe1 TDM/FDM translator is proposed which uses a periodically varying digital filter and the multiplexing weaver modulators. The general 12-Channel TDM/FDM translator using the Weaver modulators requires 24 interpolating FIR(finite impulse response) filters and 24 sinusoidal modulators, however the TDM/FDM translator proposed in this paper consists of one interpolating periodically varying digital filter and 12 sinusoidal modulators. The results obtained in this paper show that the system is simplified and the computation time is reduced. These facts are verified by the computer simulation.