• The KIPS Transactions:PartA
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• v.12A no.5 s.95
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• pp.365-374
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• 2005

Schedulability analysis is necessary to build reliable embedded real-time systems. For schedulability analysis, worst-case execution time(WCET) analysis that computes upper bounds of the execution times of tasks, is required indispensably. WCET analysis is done in two phases. The first phase is high-level analysis that analyzes control flow and finds longest paths of the program. The second phase is low-level analysis that computes execution cycles of basic blocks taking into account the hardware architecture. In this thesis, we design and implement integrated WCET analysis tools. We develop the WCET analysis tools for XScale-based system called WATER(WCET Analysis Tool for Embedded Real-time system). WATER consist of high-level flow analyzer and low-level execution time analyzer. Also, We compare real measurement for execution of program with analysis result calculated by WATER.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.148-159
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• 2005

We propose a technique for finding the worst case response time (WCRT) of a DMA request that is needed in the schedulability analysis of a whole real-time system. The technique consists of three steps. In the first step, we find the worst case bus usage pattern of each CPU task. Then in the second step, we combine the worst case bus usage pattern of CPU tasks to construct the worst case bus usage pattern of the CPU. This second step considers not only the bus requests made by CPU tasks individually but also those due to preemptions among the CPU tasks. finally, in the third step, we use the worst case bus usage pattern of the CPU to derive the WCRT of DMA requests assuming the fixed-priority bus arbitration protocol. Experimental results show that overestimation of the DMA response time by the proposed technique is within $20\%$ for most DMA request sizes and that the percentage overestimation decreases as the DMA request size increases.

• Journal of Broadcast Engineering
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• v.12 no.1 s.34
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• pp.53-60
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• 2007

A Digital Broadcasting Satellite (DBS) receiver converts digital A/V streams received from a satellite to analog NTSC A/V signals in real-time. Multi-tasking is an efficient way to improve the utilization of the processor core in real-time applications. In this paper, we propose a hybrid approach with a balanced trade-off between hardware kernel and multi-tasking programming to increase a system throughput. First, the schedulability of the critical hard real-time tasks in the DBS receiver is verified by using a simple feasibility test. Then, several soft real-time tasks are thoughtfully programmed to satisfy functional requirements of the system.

• Journal of Korea Multimedia Society
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• v.4 no.5
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• pp.371-376
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• 2001

Since continuous media such as video and audio data are displayed within a certain time constraint, their computation and manipulation should be handled under limited condition. Traditional real-time scheduling algorithms cold be directly applicable, because they are not suitable for multimedia scheduling applications which support many clients at the same time. Rate Regulating Proportional Share Scheduling Algorithm based on the stride scheduler is a scheduling algorithm considered the time constraint of the continuous media. The stride schedulers, which are designed to general tasks, guarantee the fairness of resource allocation and predictability. The key concept of RRPSSA is a rate regulator which prevents tasks from receiving more resource than its share in a given period. But this algorithm loses fairness which is a strong point of the stride schedulers, and does not show graceful degradation of performance under overloaded situation. This paper proposes a new modified algorithm, namely Modified Proportional Share Scheduling Algorithm considering the characteristics of multimedia data such as its continuity and time dependency. Proposed scheduling algorithm shows graceful degradation of performance in overloaded situation and it reduces the scheduling violations up to 70% by maintaining the fair resource allocation. The number of context switching is 8% less than RRPSSA and the overall performance is increased.

• Journal of Korean Society of Transportation
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• v.25 no.5
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• pp.161-172
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• 2007

Vehicles transporting hazardous materials can make huge damage to people, properties and environment by traffic accidents. Therefore, transporting hazardous materials is a big issue with the cutting edge technology of communications in these days. However, despite this situation, Korean government gives limited efforts for systematic management, research and investment about hazardous materials. Accordingly, this research suggests the key path finding algorithm about management of real-time schedule and routes for vehicles transporting hazardous materials. Besides, the case study is progressed in transportation networks of Seoul in order to evaluate the reality of algorithm. Specifically, time-space network transformation is performed for time window attributes. In addition, this study proposes the techniques searching for non-dominated paths considering schedule by the multiobjective shortest path algorithm based on dynamic programming in dynamic transportation networks including multiobjective attributes.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.2
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• pp.1-6
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• 2017

Due to the recent advances in IoT technologies, reducing power consumption in battery-based IoT devices becomes an important issue. An IoT device is a kind of real-time systems, and processor voltage scaling is known to be effective in reducing power consumption. However, recent research has shown that power consumption in memory increases dramatically in such systems. This paper aims at combining processor voltage scaling and low-power NVRAM technologies to reduce power consumption further. Our main idea is that if a task is schedulable in a lower voltage mode of a processor, we can expect that the task will still be schedulable even on slow NVRAM memory. We incorporate the NVRAM memory allocation problem into processor voltage scaling, and evaluate the effectiveness of the combined approach.

• Journal of Korea Society of Industrial Information Systems
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• v.29 no.3
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• pp.67-77
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• 2024

Increasing energy efficiency in factories is an activity aimed at optimizing resource allocation in manufacturing processes to establish production plans. However, this strategy may not apply effectively when night shifts are unavoidable. Additionally, continuous fluctuations in production requirements pose challenges for its implementation in the factory. Recently, with the rapid proliferation of electric vehicles (EVs), technology utilizing electric vehicle batteries as energy storage systems has gained attention. Technology using these batteries can be an alternative for factory energy management. In this paper, a factory energy management method using EV batteries is proposed. The proposed method is analyzed using PSCAD/EMTDC software, considering the state of charge of EV batteries and Time-of-Use (TOU) rates. The proposed method was compared with production scheduling established considering predicted power usage and TOU rates. As a result, production scheduling saved 4,152 KRW per day, while the proposed method saved 7,286 KRW in electricity costs. Through this paper, the possibility of utilizing EV batteries for factory energy management has been demonstrated.

• Journal of the Korea Society of Computer and Information
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• v.19 no.1
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• pp.1-8
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• 2014

In recent years, much attention has been paid to the development of intelligent vehicles that integrate automotive technology into the information technology, with the aim of improving user friendliness and stability. The representative function is a autonomous driving and a cruise control. In designing such vehicles, it is critical to address the real-time issues (i.e., real-time vehicle control and timely response). However, previous research excluded the real-time scheduling. We develop a model car with unmanned cruise control, design the real-time scheduler using cyclic executive to easily adapt the model car, and provide some insight into potential solutions based on various experiments.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.337-347
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• 2007

An embedded system is called a multi-mode embedded system if it performs multiple applications by dynamically reconfiguring the system functionality. Further, the embedded system is called a multi-mode multi-task embedded system if it additionally supports multiple tasks to be executed in a mode. In this Paper, we address a HW/SW partitioning problem, that is, HW/SW partitioning of multi-mode multi-task embedded applications with timing constraints of tasks. The objective of the optimization problem is to find a minimal total system cost of allocation/mapping of processing resources to functional modules in tasks together with a schedule that satisfies the timing constraints. The key success of solving the problem is closely related to the degree of the amount of utilization of the potential parallelism among the executions of modules. However, due to an inherently excessively large search space of the parallelism, and to make the task of schedulabilty analysis easy, the prior HW/SW partitioning methods have not been able to fully exploit the potential parallel execution of modules. To overcome the limitation, we propose a set of comprehensive HW/SW partitioning techniques which solve the three subproblems of the partitioning problem simultaneously: (1) allocation of processing resources, (2) mapping the processing resources to the modules in tasks, and (3) determining an execution schedule of modules. Specifically, based on a precise measurement on the parallel execution and schedulability of modules, we develop a stepwise refinement partitioning technique for single-mode multi-task applications. The proposed techniques is then extended to solve the HW/SW partitioning problem of multi-mode multi-task applications. From experiments with a set of real-life applications, it is shown that the proposed techniques are able to reduce the implementation cost by 19.0% and 17.0% for single- and multi-mode multi-task applications over that by the conventional method, respectively.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.913-915
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• 2005

실시간 시스템에서는 두 개 이상의 태스크가 공유자원을 사용한다. 이러한 자원에 의해서 높은 우선순위 태스크가 낮은 우선순위 태스크에 의해서 CPU를 점유 당하는 우선순위 역전현상(Priority Inversion)이 발생한다. 우선순위 역전 문제는 실시간 시스템의 스케줄 가능성과 예측성에 심각한 결함을 야기할 수 있다. 이를 해결하기 위해 본 논문에서는 비교적 크기가 작으면서도 실시간 운영체제의 핵심적 특징을 잘 갖추고 있는 $iRTOS^{TM}$ 커널을 사용하였고 우선순위 역전을 해결하기 위해서 Priority Inheritance Protocol을 사용하여 확장된 MuTexS를 구현하였다.