• Journal of the Korean School Mathematics Society
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• v.8 no.4
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• pp.481-494
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• 2005

In this study, the goal is to spread profound knowledge and theory through providing with accumulated methods in mathematics education to the students who are relatively neglected in educational benefits. The process is divided into 3 categories: mathematics for obtaining common sense and intelligence, practical math for application, and math as a liberal art to elevate their characters. Furthermore, it includes the reasons for studying math, improving problem-solving skills, machinery application learning, introduction to code(cipher) theory and game theory, utilizing GSP to geometry learning, and mathematical relations to sports and art. Based on these materials, the next step(goal) is to train graduate students to conduct researches in teaching according to the teaching plan, as well as developing interesting and effective teaching plan for the remote high school learners.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.21-32
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• 2006

A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.209-209
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• 2010

단위면적 당 메모리 집적도를 높이기 위해 플래시 기억소자의 크기를 줄일 때, 절연층 두께 감소에 의한 누설 전류의 발생, 단채널 효과 및 협폭 효과와 같은 문제 때문에 소자 크기의 축소가 한계에 도달하고 있다. 이러한 문제점들을 개선하기 위해 본 연구에서는 FinFET구조위에 Oxide-Nitride-Oxide (ONO) 층을 적층하여 2-비트 특성을 갖는 플래시 메모리 소자를 제안하였다. 소자의 작동전압을 크게 줄일 수 있으며 소자의 크기가 작아질 때 일어나는 단채널 효과의 문제점을 해결할 수 있는 FinFET 구조를 가진 기억소자에서 제어게이트를 제어게이트1과 제어게이트2로 나누어 독립적으로 쓰기 및 소거 동작하도록 하였다. 2-비트 동작을 위해 제어 게이트1의 게이트 절연막의 두께를 제어게이트2의 게이트 절연막의 두께보다 더 얇게 함으로써 두 제어게이트 사이의 coupling ratio를 다르게 하였다. 제어게이트1의 트랩층의 두께를 제어게이트2의 트랩층의 두께보다 크게 하여 제어게이트1의 트랩층에 더 많은 양의 전하가 포획될 수 있도록 하였다. 제안한 기억소자가 2-비트 동작하는 것을 확인 하기위하여 2차원 시뮬레이션툴인 MEDICI를 사용하여 제시한 FinFET 구조를 가진 기억소자의 전기적 특성을 시뮬레이션하였다. 시뮬레이션을 통해 얻은 2-비트에 대한 각 상태에서 각 전하 포획 층에 포획된 전하량의 비교를 통해서 coupling ratio 차이와 전하 포획층의 두께 차이로 인해 포획되는 전하량이 달라졌다. 각 상태에서 제어게이트에 읽기 전압을 인가하여 전류-전압 특성 곡선을 얻었으며, 각 상태에서의 문턱전압들이 잘 구분됨을 확인함으로써 제안한 FinFET 구조를 가진 플래시 메모리 소자가 셀 당 2-비트 동작됨을 알 수 있었다.

• Journal of Korea Society of Industrial Information Systems
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• v.9 no.2
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• pp.44-50
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• 2004

Recently, as the number of entities participating in the Grid system increased, the response time of LDAP system became inadequate. Consequently, we have to design new LDAP that suitable for high performance Grid environments. For this, researches about analysis of performance LDAP system are needed firstly. However, because researches are focused mostly on read operation optimized environments, so these result of researches are not directly applied to high performance Grid environments that write operation occupies most. In this paper, we provide overall results of analysis of performance of distributed directory system. The analysis is based on an analytic performance model by applying the M/M/1 queuing model. Finally, based on the results, we suggest the direction for the design of high performance LDAP system and this research results can be applied as basic materials to design of GIS in high performance Grid environments as well as.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.4
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• pp.919-928
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• 2018

Out-Of-Bounds (OOB) is one of the most powerful vulnerabilities in heap memory. The OOB vulnerability allows an attacker to exploit unauthorized access to confidential information by tricking the length of the array and reading or writing memory of that length. In this paper, we propose a method to automatically detect OOB vulnerabilities in heap memory using dynamic symbol execution and shadow memory table. First, a shadow memory table is constructed by hooking heap memory allocation and release function. Then, when a memory access occurs, it is judged whether OOB can occur by referencing the shadow memory, and a test case for causing a crash is automatically generated if there is a possibility of occurrence. Using the proposed method, if a weak block search is successful, it is possible to generate a test case that induces an OOB. In addition, unlike traditional dynamic symbol execution, exploitation of vulnerabilities is possible without setting clear target points.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.9
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• pp.457-464
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• 2005

In this paper a 3D memory system that allows 17 access types at an arbitrary position is introduced. The proposed memory system is based on two main functions: memory module assignment function and address assignment function. Based on them, the memory system supports 17 access types: 13 Lines, 3 Rectangles, and 1 Hexahedron. That is, the memory system allows simultaneous access to multiple data in any access types at an arbitrary position with a constant interval. In order to allow 17 access types the memory system consists of memory module selection circuitry, data routing circuitry for READ/WRITE, and address calculation/routing circuitry In the point of view of a developer and a programmer, the memory system proposed in this paper supports easy hardware extension according to the applications and both of them to deal with it as a logical three-dimensional away In addition, multiple data in various across types can be simultaneously accessed with a constant interval. Therefore, the memory system is suitable for building systems related to ,3D applications (e.g. volume rendering and volume clipping) and a frame buffer for multi-resolution.

• Journal of the Korea Society of Computer and Information
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• v.25 no.4
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• pp.1-9
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• 2020

In this paper, we propose Dynamic Rank Subsetting (DRAS) technique that enhances the energy-efficiency and the performance of memory system through the data compression. The goal of this technique is to enable a partial chip access by storing data in a compressed format within a subset of DRAM chips. To this end, a memory rank is dynamically configured to two independent sub-ranks. When writing a data block, it is compressed with a data compression algorithm and stored in one of the two sub-ranks. To service a memory request for the compressed data, only a sub-rank is accessed, whereas, for a memory request for the uncompressed data, two sub-ranks are accessed as done in the conventional memory systems. Since DRAS technique requires minimal hardware modification, it can be used in the conventional memory systems with low hardware overheads. Through experimental evaluation with a memory simulator, we show that the proposed technique improves the performance of the memory system by 12% on average and reduces the power consumption of memory system by 24% on average.

• Journal of KIISE:Databases
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• v.34 no.2
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• pp.133-140
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• 2007

Flash memory has penetrated our life in various forms. For example, flash memory is important storage component of ubiquitous computing or mobile products such as cell phone, MP3 player, PDA, and portable storage kits. Behind of the wide acceptance as memory is many advantages of flash memory: for instances, low power consumption, nonvolatile, stability and portability. In addition to mentioned strengths, the recent development of gigabyte range capacity flash memory makes a careful prediction that the flash memory might replace some of storage area dominated by hard disks. In order to have overwriting function, one block must be erased before overwriting is performed. This difference results in the cost of reading, writing and erasing in flash memory[1][5][6]. Since this difference has not been considered in traditional buffer replacement technologies adopted in system software such as OS and DBMS, a new buffer replacement strategy becomes necessary. In this paper, a new buffer replacement strategy, reflecting difference I/O cost and applicable to flash memory, suggest and compares with other buffer replacement strategies using workloads as Zipfian distribution and real data.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06a
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• pp.200-202
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• 2012

공정기술의 발달로 인해 GPU는 빠르게 발전하고 있다. GPU는 영상처리뿐만 아니라 한 번에 많은 양의 데이터를 처리하는 범용 작업에도 많이 쓰이고 있다. 한편, 최근에는 3차원으로 코어를 적층하는 3차원 CPU구조에 대해 많은 연구가 수행되고 있다. 3차원 구조는 코어를 수직으로 적층시켜 내부 연결망의 길이를 크게 줄여주어 성능을 크게 개선하는 장점을 가지고 있다. 이를 반영하여 GPU에도 3차원 구조를 적용하여 GPU의 성능을 향상시키려는 선행연구에 맞춰 본 논문에서는 3차원 구조 GPU의 성능 향상을 저해하는 요소들에 대해서 분석해 보고자한다. 본 논문에서는 선행연구에서 밝힌 메모리 인터페이스에서 발생하는 병목현상 이외에도 주 메모리 큐 용량과 네트워크 방식에 따른 3차원 GPU의 성능향상을 실험을 통하여 알아본다. 실험 결과 주 메모리 큐 용량에 따른 3차원 GPU의 IPC는 가장 큰 사이즈와 가장 작은 사이즈의 차이가 4 미만으로 주 메모리 큐 용량은 3차원 GPU의 성능에 큰 영향을 미치지 않는 것으로 분석된다. 주 메모리로의 읽기 또는 쓰기 요청들을 순서대로 저장하는 큐의 역할이 3차원 구조 GPU의 동작에는 큰 영향을 미치지 않기 때문으로 분석된다. 반면 네트워크 방식에 따른 실험에서는 fly 네트워크 방식에 비해서 crossbar 네트워크 방식이 더 빠른 데이터 통신을 가능하게 해주어 crossbar네트워크 방식에서 IPC수치가 약 14 증가함을 알 수 있다. 두 가지 실험을 통하여 3차원 GPU의 성능에 네트워크 방식 차이가 주 메모리 큐 용량 변화보다 더 큰 영향을 주는 것을 확인할 수 있다.

• Journal of the Korea Computer Industry Society
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• v.7 no.5
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• pp.481-486
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• 2006

Whereas conveniences deriving from the development of information and telecommunication technology increase, information outflow and illegal data use are also rapidly on the rise. Consequently, many studies to prevent illegal information outflow are currently under way, and the use of Smart Card is in steep jump. Recently, Java Card is diffused fast as an alternative to complement the technical problems of the Smart Card. This paper designed and Implementation the system for multi-users authentication and file access control by user through designing a Java Card applet that is used for information protection and in various application fields. For allowing a file access competence, each user's file access competence is processed via drawing up the access condition table in the applet. Therefore, illegal correction exposure and destruction of information, which become the concerns when multi-users have an access, can be prevented. In addition its application becomes possible in the system requiring multi-users certifications.