• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.20-27
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• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.649-652
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• 2013

LEON3 is a 32-bit synthesisable processor based on the SPARC V8. It can be connected to AMBA 2.0 bus and has a 7-stage pipeline, IEEE-754 FPU and 256[KB] cache. It can be easily implemented using FPGA and used for a SoC design. DSU which comes with LEON3 can be used to control and monitor the operation of LEON3. And DSU makes it easy to set a debugging environment for the development of both hardware and software for an embedded systems based on LEON3. This paper presents the summary of the development of LEON3 monitoring software.

• 전자공학회논문지 IE
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• v.45 no.4
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• pp.27-32
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• 2008

This paper presents the implementation of simple genetic algorithm using hardware description language for evolvable hardware embedded system. Evolvable hardware refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. So, it is especially suited to applications where no hardware specifications can be given in advance. Evolvable hardware is based on the idea of combining reconfigurable hardware device with evolutionary computation, such as genetic algorithm. Because of parallel, no function call overhead and pipelining, a hardware genetic algorithm give speedup over a software genetic algorithm. This paper suggests the hardware genetic algorithm for evolvable embedded system chip. That includes simulation results for several fitness functions.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2015.07a
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• pp.489-490
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• 2015

객체의 인식을 위한 컴퓨터 비전 알고리즘은 안개와 비와 같은 기상이 좋지 않은 상황에서는 인식 성능이 떨어지고 있다. 이로 인하여 최근 악천후 환경에서 촬영된 영상으로부터 날씨 현상을 제거하는 기법들이 연구되고 있다. 빗줄기는 시공간적 무작위성으로 인하여 검출 및 제거가 어려운 현상이다. 또한 기존의 빗줄기 검출 및 제거 기법들은 대부분 고정된 카메라로부터 촬영된 영상을 대상으로 처리함으로써 자동차와 같은 움직임이 있는 촬영환경에서는 부적합하다. 최근에는 카메라나 객체의 움직임에 대응할 수 있는 빗줄기 검출 및 제거 알고리즘이 개발되고 있으나, 방대한 연산량이 필요하기 때문에 실시간이 불가능하다. 본 논문에서는 최근 연구되고 있는 카메라 움직임이 있는 환경에서 빗줄기 검출 및 제거 알고리즘을 DSP 환경에서 구현하고 내부 메모리 최적화와 EMDA 이용, 소프트웨어 파이프라인 등을 통해 최적화를 수행하여 실시간성을 보인다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.11
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• pp.1377-1383
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• 2019

Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.6
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• pp.1214-1219
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• 2009

Many studies are being applied for various parts of USN (Ubiquitous Sensor Network) technology. The world's large retail stores and warehouses that apply logistic management are also studied. With this, USN technology is increasing in its utilization. However, to handle and process real-time data will never be never easy if these huge warehouses are using too many sensors, and real-time data correction is almost impossible. Software implementation and high-speed hardware are insufficient to solve these complex problems. To solve this problem, a key solution is to implement high-speed software. Hence, this paper suggests a USN logistics management system that applies pipelining techniques for efficiency in real-time data correction and reduces errors of generated values.

• KIPS Transactions on Software and Data Engineering
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• v.2 no.2
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• pp.123-130
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• 2013

As size of genomic data is increasing rapidly, the needs for high-performance computing system to process and store genomic data is also increasing. In this paper, we captured I/O trace of a system which analyzed 500 million sequence reads data in Genome analysis pipeline for 86 hours. The workload created 630 file with size of 1031.7 Gbyte and deleted 535 file with size of 91.4 GByte. What is interesting in this workload is that 80% of all accesses are from only two files among 654 files in the system. Size of read and write request in the workload was larger than 512 KByte and 1 Mbyte, respectively. Majority of read write operations show random and sequential patterns, respectively. Throughput and bandwidth observed in each processing phase was different from each other.

• Journal of Broadcast Engineering
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• v.27 no.3
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• pp.308-317
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• 2022

Researches are underway to efficiently reduce the size of video data transmitted and stored in the image analysis process using deep learning-based machine vision technology. MPEG (Moving Picture Expert Group) has newly established a standardization project called VCM (Video Coding for Machine) and is conducting research on video encoding for machines rather than video encoding for humans. We are researching a multitask that performs various tasks with one image input. The proposed pipeline does not perform all object detection of each task that should precede object detection, but precedes it only once and uses the result as an input for each task. In this paper, we propose a pipeline for efficient multitasking and perform comparative experiments on compression efficiency, execution time, and result accuracy of the input image to check the efficiency. As a result of the experiment, the capacity of the input image decreased by more than 97.5%, while the accuracy of the result decreased slightly, confirming the possibility of efficient multitasking.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2022.06a
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• pp.269-270
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• 2022

자율주행 자동차의 개발을 위해서는 다양한 기능 평가, 성능 평가, 안전성 평가 등이 필수적이다. 이러한 평가는 컴퓨터 시뮬레이션과 실제 주행을 통해 이뤄질 수 있으며, 현실의 도로 상황을 고려한 단위시험환경들을 조합 구성한 통합시험환경에서 수행하는 것이 일반적이다. 여기서 단위시험환경은 도로망 구성, 장애물, 표지판 등의 정보를 포함하는 정밀도로지도를 기반으로 주행차량수, 보행자, 기상환경, 동적 이벤트 요소 등을 고려하여 구성할 수 있다. 본 논문에서는 이러한 단위시험환경을 구성하기 위한 정밀도로지도 처리 방법을 소개한다. 구체적으로는 정밀도로지도 처리를 포함하는 데이터 파이프라인을 설계하고, 정밀도로지도 객체분석을 통해 시험환경의 특성 및 상호 유사성을 파악한다. 국토지리정보원에서 배포한 정밀도로지도를 사용하여 객체를 추출하고 분석하는 실험을 수행했으며 전반적인 동작 상태를 확인했다. 개발한 소프트웨어는 향후 자율주행 학습을 위한 단위 및 통합 시험환경 구축 및 법규 및 규제 대응 서비스 시나리오의 구성에 활용할 예정이다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.96-105
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• 2015

This paper proposes a DSP optimization solution of rain detection and removal algorithm. We propose rain detection and removal algorithms considering camera motion, and also presents optimization results in algorithm level and DSP level. At algorithm level, this paper utilizes a block level binary pattern analysis, and reduces the operation time by using the fast motion estimation algorithm. Also, the algorithm is optimized at DSP level through inter memory optimization, EDMA, and software pipelining for real-time operation. Experiment results show that the proposed algorithm is superior to the other algorithms in terms of visual quality as well as processing speed.