• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.561-564
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• 2009

This paper present design and implementation of U-city infrared image surveillance system based on the digital media processor. The hardware is designed and implemented by using commercial chips such as DM642 processor and video encoder, video decoder and the functions of software are to analyze temperature distribution of a monitoring image and to monitor disaster situation such as fire. The required functions and performances are confirmed by testing of the prototype and we verified practicality of the system.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.07a
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• pp.453-456
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• 2012

최근 멀티코어 프로세서의 사용이 증가함에 따라 영상처리나 대용량 처리가 필요한 기술과 같은 다양한 분야에 OpenMP, SIMD 등과 같은 다양한 병렬화 기법들이 적용되고 있다. 특히, 영상처리 분야에서 Full-HD, UHD, 3D TV 등과 같이 높은 복잡도를 갖는 컨텐츠들의 수요가 높아짐에 따라 기존의 싱글코어 기반의 코덱에 병렬화를 적용하는 여러가지 기법들이 제안되어왔다. 본 논문은 기존의 OpenMP와 SIMD와 같은 병렬처리 기법을 H.264/AVC 코덱의 참조 소프트웨어 JM 18.2의 디코더에 적용함으로써 Full-HD영상을 실시간으로 디코딩하는 기법을 제안한다. 실험결과는 평균 38.338 fps의 프레임 율을 보이며 병렬처리시 평균 2배 이상 프레임 율이 증가함으로써 Full-HD 영상의 실시간 처리가 가능하다는 것을 보여준다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.3
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• pp.841-846
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• 2010

This paper presents design and implementation of an intelligent video surveillance system. The proposed system has advantages of management efficiency and operation robustness unrelated to working condition compared to conventional CCTV based system. The system hardware is designed and implemented by using commercial chips such as digital media processor and video encoder, video decoder and the functions of software are to analyze temperature distribution of a infrared image and to detect disaster situation such as fire. The required functions are confirmed by testing of the prototype and we verified practicality of the system.

• Journal of the Korea Computer Graphics Society
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• v.27 no.5
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• pp.33-43
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• 2021

In this paper, we propose a framework that transfers the information of style motions to content motions based on a variational autoencoder network combined with a style encoding in the latent space. Because we transfer a style to a content motion that is sampled from a variational autoencoder, we can increase the diversity of existing motion data. In addition, we can improve the unnatural motions caused by decoding a new latent variable from style transfer. That improvement was achieved by additionally using the velocity information of motions when generating next frames.

• Korean Journal of Cognitive Science
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• v.34 no.3
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• pp.197-226
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• 2023

Generative Text Summarization is one of the Natural Language Processing tasks. It generates a short abbreviated summary while preserving the content of the long text. ROUGE is a widely used lexical-overlap based metric for text summarization models in generative summarization benchmarks. Although it shows very high performance, the studies report that 30% of the generated summary and the text are still inconsistent. This paper proposes a methodology for evaluating the performance of the summary model without using the correct summary. AggreFACT is a human-annotated dataset that classifies the types of errors in neural text summarization models. Among all the test candidates, the two cases, generation summary, and when errors occurred throughout the summary showed the highest correlation results. We observed that the proposed evaluation score showed a high correlation with models finetuned with BART and PEGASUS, which is pretrained with a large-scale Transformer structure.

• Journal of KIISE:Software and Applications
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• v.37 no.5
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• pp.354-362
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• 2010

This paper proposes a new method for a hierarchical analysis of human gait by dividing the motion into gait direction and gait posture using the tool of dynamic Bayesian network. Based on Factorial HMM (FHMM), which is a type of DBN, we design the Gait Motion Decoder (GMD) in a circular architecture of state space, which fits nicely to human walking behavior. Most previous studies focused on human identification and were limited in certain viewing angles and forwent modeling of the walking action. But this work makes an explicit and separate modeling of pedestrian pose and posture to recognize gait direction and detect orientation change. Experimental results showed 96.5% in pose identification. The work is among the first efforts to analyze gait motions into gait pose and gait posture, and it could be applied to a broad class of human activities in a number of situations.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.165-174
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• 2010

The H.264/AVC standard obtained better performance than previous compression standards, but it also increased the computational complexity of CODEC simultaneously. Various techniques recently included at the KTA software developed by VCEG also were increasing its complexity. Especially adaptive interpolation filter has more complexity than two times due to development for coding efficiency. In this paper, we propose low-complexity filter bank to improve speed up of decoding and coding gain. We consists of filter bank of a fixed-simple filter for low-complexity and adaptive interpolation filter for high coding efficiency. Then we compensated using optimal filter at each macroblock-level or frame-level. Experimental results shows a similar coding efficiency compared to existing adaptive interpolation filter and decoding speed of approximately 12% of the entire decoder gained.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3653-3659
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• 2009

Inter-prediction is always the main bottleneck in H.264/AVC baseline profile. This paper describes an efficient inter-prediction hardware architecture design. H.264/AVC decoder supports various block types but reference software considers only the $4{\times}4$ block when the reference block is being fetched. This causes duplicated pixels which needs extra fetch cycles. In order to eliminate some of the duplicated pixels, the $8{\times}8$ and $4{\times}4$ blocks were considered in the previous design. If the block size is larger than or equal to the $8{\times}8$ block, it will be decomposed into several $8{\times}8$ blocks and if the block size is smaller than the $8{\times}8$ block it will be decomposed into several $4{\times}4$ blocks. Comparing with the reference software, the maximum and minimum cycle reduction of the previous design are 41.5% and 28.2% respectively. For further reduction of the fetch cycles, the various block types are considered in this paper. As a result, the maximum cycle reduction is 18.6% comparing with the previous design.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.12
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• pp.867-879
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• 2006

This paper concerns fast and time accurate HW/SW cosimulation for MPSoC(Multi-Processor System-on-chip) architecture where multiple software and/or hardware components exist. It is becoming more and more common to use MPSoC architecture to design complex embedded systems. In cosimulation of such architecture, as the number of the component simulators participating in the cosimulation increases, the time synchronization overhead among simulators increases, thereby resulting in low overall cosimulation performance. Although SystemC cosimulation frameworks show high cosimulation performance, it is in inverse proportion to the number of simulators. In this paper, we extend the novel technique, called virtual synchronization, which boosts cosimulation speed by reducing time synchronization overhead: (1) SystemC simulation is supported seamlessly in the virtual synchronization framework without requiring the modification on SystemC kernel (2) Parallel execution of component simulators with virtual synchronization is supported. We compared the performance and accuracy of the proposed parallel SystemC cosimulation framework with MaxSim, a well-known commercial SystemC cosimulation framework, and the proposed one showed 11 times faster performance for H.263 decoder example, while the accuracy was maintained below 5%.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.