• Journal of KIISE:Computing Practices and Letters
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• 제15권7호
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• pp.469-477
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• 2009

In mobile systems, energy efficiency is critical to extend battery life. Therefore, power consumption should be taken into account to develop software in addition to performance, Efficient software design in power and performance is possible if accurate power prediction is accomplished during the execution of software, In this paper, power estimation model is developed using statistical analysis, The proposed model analyzes processor behavior Quantitatively using the data of performance monitoring events and power consumption collected by executing various benchmark programs, And then representative hardware events on power consumption are selected using hierarchical clustering, The power prediction model is established by regression analysis in which the selected events are independent variables and power is a response variable, The proposed model is applied to a PXA320 mobile processor based on Intel XScale architecture and shows average estimation error within 4% of the actual measured power consumption of the processor.

• The KIPS Transactions:PartD
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• 제18D권1호
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• pp.45-56
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• 2011

The importance of low-power embedded system is being increased. The studies on low-power system have been performed in issues of hardware architecture and operating system. However because the behaviors of software control the working of hardware devices, the power analysis of software is one of critical issues in energy-efficient embedded system development. This paper proposes a technique to extract tasks from software design models with considering power consumption. We first define the criteria for task extraction, and then propose the way to separate out the task from UML 2.0 design models. Our technique can provide the chance to reduce the power consumption as well as to fulfill the performance requirement in the early phase of software development.

• Journal of Korea Game Society
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• 제17권4호
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• pp.137-148
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• 2017

Since the power consumption of data centers is large and computer serves take a large portion of it, there have been much research on the power saving of servers in various ways recently. Among the units of severs CPU is one of major power consuming units. In this paper, a method of client-server assignment for minimizing the CPU power consumption of servers in a game server cluster is proposed. We model the client-server assignment problem as an optimization problem, and find a solution to the problem using a simulated annealing-based technique. One of major features of our method is to select a proper operating frequency according to the amount of load on a server. The selection of a lower frequency in case of low load will result in reducing power consumption. To our survey, little research on client-server assignment in consideration of power consumption has been carried out.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제13권1호
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• pp.170-176
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• 2009

The efficiently power management is an important requirement traditionally in the mobile communication system which uses battery as their power source. Especially, it has been emphasized in the most devices, which has to provide high performance and various functions with an extended operating time. In this article, the adaptive power management technique for the core CPU unit in Embedded systems used widely for the mobile system thanks to its advantage on power consumption and physical size, is proposed.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.1119-1120
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• 2008

The efficiently power management is an important requirement traditionally in the mobile communication system which uses battery as their power source. Especially, it has been emphasized in the most recent devices, which has to provide high performance and various functions with an extended operating time. In this article, the adaptive power management technique for the core processor unit in embedded systems used widely for the mobile system thanks to its advantage on power consumption and physical size, is proposed.

• Journal of KIISE:Computer Systems and Theory
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• 제30권12호
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• pp.724-735
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• 2003

In recent high-performance superscalar processors, the result value of an instruction is predicted to improve instruction-level parallelism by breaking data dependencies. Using those predicted values, instructions are speculatively executed and substantial performance can be gained. It, however, requires additional power consumption due to the frequent access and update of the value prediction table. In this paper, first, the trade-off between the performance improvement and the increased power consumption for value prediction is measured and analyzed. And, in order to reduce additional power consumption without performance loss, the technique of controlling speculative execution with confidence counter and predicting useful instructions is developed. Also, in order to prove the validity, a tool is developed that can simulate processor behavior at cycle-level and measure total energy consumption and power consumption per cycle.

• Journal of Korea Society of Industrial Information Systems
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• 제28권1호
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• pp.17-25
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• 2023

As the range of use of urban unmanned aerial vehicles (UAV) expands, it is necessary to operate UAVs efficiently because of its limited battery capacity. For this, it is required to find the optimal flight profile with various simulations. Therefore, it is important to predict the power and energy consumption of the UAV battery. In this paper, we analyzed the relationship between the speed and acceleration of the UAV and power consumption during the flight. Then, we derived a linear model, which is easily utilized. In addition, we also derived an accurate power consumption model based on deep neural network learning. To find the efficient model, we used learning data as 1) the GPS 3-axis velocity and acceleration data, 2) the IMU 3-axis velocity only, and 3) the IMU 3-axis velocity and acceleration data. The final model shows 5.86% error rate for power consumption and 1.50% error rate for the cumulative energy consumption.

• Proceedings of the Korea Information Processing Society Conference
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• 한국정보처리학회 2008년도 춘계학술발표대회
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• pp.532-535
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• 2008

내장형 시스템에서 캐시 메모리는 시스템의 성능과 전력 소모에 매우 큰 비중을 차지한다. 일반적인 내장형 시스템에 적용되는 집합 연관 구조 캐시는 모든 웨이에 전력을 공급해야 하므로 전력 소모 효율성이 매우 낮다. 이러한 단점을 보완하기 위해 순차 접근 캐시는 데이터가 존재하는 하나의 캐시만 항상 전력을 공급하게 하는 구조를 제안하지만 모든 작업에 1사이클이 더 소모되는 단점을 갖는다. 캐시 웨이 예측 기법은 적중 시 1사이클의 시간에 1개의 웨이에 만 전력을 공급하게 하는 최상의 구조를 갖지만 적중 실패 시 일반적인 집합 연관 구조보다 1사이클이 더 소모되고 똑같은 전력 소비를 가져오는 단점을 갖는다. 본 논문에서는 이 두 구조의 절충안을 통해 데이터 적중 시 웨이 예측 기법과 같은 성능을 가지며 실패 시에도 순차 접근 캐시와 동일한 성능을 보이는 새로운 내장형 시스템을 위한 저전력 캐시 구조를 제안한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제41권10호
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• pp.95-104
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• 2004

This paper propose a motion estimator architecture to reduce the power consumption of the most-power-consuming motion estimation method when designing multimedia SoC with deep submicron technologies below 0.13${\mu}{\textrm}{m}$. The proposed architecture considers both dynamic and static power consumption so that it is suitable for large leakage process technologies, while conventional architectures consider only dynamic power consumption. Consequently, it is suitable for mobile information terminals such as mobile videophone where efficient power management is essential. It exploits full search method for simple hardware implementation. It also exploits early break-off method to reduce dynamic power consumption. To reduce static power consumption, megablock shutdown method considering power line noise is also employed. To evaluate the proposed architecture when applied multimedia SoC, system-level control flow and low-power control algorithm are developed and the power consumption was calculated based on thor From the simulation results, power consumption was reduced to about 60%. Considering the line width reduction and increased leakage current due to heat dissipation in chip core, the proposed architecture shows steady power reduction while it goes worse in conventional architectures.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제29권1C호
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• pp.149-156
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• 2004

In this paper, novel power-aware motion estimation is proposed for low-power multimedia communication. In the video compression, motion estimation dominates the total power consumption, where better performance usually requires more power consumption. Among several motion estimation algorithms with different performance and power, the proposed motion estimation adaptively selects the optimal algorithm during run-time, considering the trade-off between performance and power. The proposed motion estimation can be easily applied to various motion estimation algorithms with negligible computation or hardware overhead. According to simulation results, the proposed motion estimation reduces the power consumption to 1/15.7~1/5.6 without performance degradation, when compared to the conventional algorithms.