• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.16-21
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• 2007

CMOS variable gain amplifier (VGA) IC designs for the structure monitoring systems of the telemetries were developed. A three stage cascaded VGA using a differential amplifier and a linear-in-dB controller is presented. A proposed VGA is a modified version of a conventional VGA such that the gain is controlled in a linear-in-dB fashion through the current ratio. The proposed VGA circuit introduced in this paper has a dynamic range of 77 dB with 1.5 dB gain steps. It also achieved a gain error of less than 1.5 dB over 77 dB gain range. The VGA can operate up to 10MHz dissipating 13.8 mW from a single 1.8 V supply. The core area of the VGA fabricated in a Magnachip $0.18{\mu}m$ standard CMOS process was about $430{\mu}m{\times}350{\mu}m$. According to measurement results, we can verify that the proposed method is reasonable with regard to the enhancement of dynamic range and the better linear-in-dB characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.673-684
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome this problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. Using the proposed gain control scheme, a low-voltage and high-speed CMOS VGA is designed. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than l.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$${\times}$360${\mu}{\textrm}{m}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.83-89
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• 2006

This paper describes the design of I/Q channel 12bit Digital-to-Analog Converter(DAC) which shows the conversion rate of 120MHz and the power supply of 3.3V with 0.35um CMOS n-well 1-poly 4-metal process for advanced wireless transceiver. The proposed DAC utilizes 4-bit thermometer decoder with 3 stages for minimum glitch energy and linearity error. Also, using a optimized 4bit thermometer decoder for the decrement of the chip area. Integral nonlinearity(INL) of ${\pm}1.6LSB$ and differential nonlinearity(DNL) of ${\pm}1.3LSB$ have been measured. In single tone test, the ENOB of the proposed 12bit DAC is 10.5bit and SFDR of 73dB(@ Fs=120MHz, Fin=1MHz) is measured, respectively. Dual-tone test SFDR is 61 dB (@ Fs=100MHz, Fin=1.5MHz, 2MHz). Glitch energy of 31 pV.s is measured. The converter consumes a total of 105mW from 3.3-V power supply.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.53-53
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• 1999

전계방출을 이용한 평판 표시장치는 CRT가 가진 장점을 모두 갖는 동시에 얇고 가벼우며 낮은 전력소모로 완벽한 색을 구현할 수 있는 차세대 표시장치로서 이에 대한 여국가 활발히 이루어지고 있다. 여기에 사용되는 음극물질로서 실리콘이나 몰리 등을 팁모양으로 제작하여 사용해 왔다. 하지만 잔류가스에 의한 역스퍼터링이나 화학적 반응에 의해서 전계방출 성능이 점차 저하되는 등의 해결해야할 많은 문제가 있다. 이러한 문제들을 해결하기 위하여 탄소계 재료로서 다이아몬드, 다이아몬드상 카본 등을 이용하려는 노력이 진행되어 왔다. 이중 유리화 비정형 탄소는 다량의 결함을 가지고 있는 유리질의 고상 탄소 재로로서, 전기전도도가 우수하면서 outgassing이 적고 기계적 강도가 뛰어나며 고온에서도 화학적으로 안정하여 전계방출 소자의 음극재료로서 알맞은 것으로 생각된다. 유리화 비정형 탄소가루를 전기영동법으로 기판에 코팅하여 전계방출 소자를 제작하였다. 전기영동 용액으로 이소프로필알코올에 질산마그네슘과 소량의 증류수, 유리화 비정형 탄소분말을 섞어주었고 기판으로는 몰리(Mo)가 증착된 유리를 사용하였다. 균일한 증착을 위해서 증착후 역전압을 걸어 주는 방법과 증착 후 플라즈마 처리를 하는 등의 여러 가지 방법을 사용했다. 전계방출 전류는 1$\times$10-7Torr이사에서 측정하였다. 1회 제작된 용액으로 반복해서 증착한 횟수에 따라 표면의 거치기, 입자의 분포, 전계방출 측정 결과 등의 차이가 관찰되었다. 발광이미지는 전압에 따라 변화하였고, 균일한 발광을 관찰하기 위해서 오랜 시간동안 aging 과정을 거쳐야 했다. 그리고 구 모양의 양극을 사용해서 위치를 변화시키며 시동 전기장을 관찰하여 위치에 따른 전계방출의 차이를 조사하여 발광의 균일성을 알 수 있었다.on microscopy로 분석하였으며 구조 분석은 X-선 회절분석, X-ray photoelectron spectroscopy 그리고Auger electron spectroscope로 하였다. 증착된 산화바나듐 박막의 전기화학적 특성을 분석하기 위하여 리튬 메탈을 anode로 하고 EC:DMC=1:1, 1M LiPF6 액체 전해질을 사용한 Half-Cell를 구성하여 200회 이상의 정전류 충 방전 시험을 행하였다. Half-Cell test 결과 박막의 결정성과 표면상태에 따라 매우 다른 전지 특성을 나타내었다.도상승율을 갖는 경우가 다른 베이킹 시나리오 모델에 비해 효과적이라 생각되며 초대 필요 공급열량은 200kW 정도로 산출되었다. 실질적인 수치를 얻기 위해 보다 고차원 모델로의 해석이 필요하리라 생각된다. 끝으로 장기적인 관점에서 KSTAR 장치의 베이킹 계획도 살펴본다.습파라미터와 더불어, 본 연구에서 새롭게 제시된 주기분할층의 파라미터들이 모형의 학습성과를 높이기 위해 함께 고려된다. 한편, 이러한 학습과정에서 추가적으로 고려해야 할 파라미터 갯수가 증가함에 따라서, 본 모델의 학습성과가 local minimum에 빠지는 문제점이 발생될 수 있다. 즉, 웨이블릿분석과 인공신경망모형을 모두 전역적으로 최적화시켜야 하는 문제가 발생한다. 본 연구에서는 이 문제를 해결하기 위해서, 최근 local minimum의 가능성을 최소화하여 전역적인 학습성과를 높여 주는 인공지능기법으로서 유전자알고리즘기법을 본 연구이 통합모델에 반영하였다. 이에 대한 실증사례 분석결과는 일일 환율예측문제를 적용하였을 경우, 기존의 방법론보다 더 나운 예측성과를 타나내었다.pective" to workflow architectural discussions. The vocabulary suggested

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.7-14
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• 2008

In this paper, we designed the HVIC(High Voltage Gate Driver IC) which has improved noise immunity characteristics and high driving capability. Operating frequency and input voltage range of the designed HVIC is up to 500kHz and 650V, respectively. Noise protection and schmitt trigger circuit is included in the high-side level shifter of designed IC which has very high dv/dt noise immunity characteristic(up to 50V/ns). And also, rower dissipation of high-side level shifter with designed short-pulse generation circuit decreased more that 40% compare with conventional circuit. In addition, designed HVIC includes protection and UVLO circuit to prevent cross-conduction of power switch and sense power supply voltage of driving section, respectively. Protection and UVLO circuit can improve the stability of the designed HVIC. Spectre and Pspice circuit simulator were used to verify the operating characteristics of the designed HVIC.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.43-55
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome the problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. The proposed gain control scheme makes it easy to implement a low-voltage and high-speed VGA. This paper describes the problems existed in conventional methods, the principle and advantages of the proposed scheme, and their performance comparison in detail. A CMOS VGA cell is designed using the proposed degeneration resistor. The 3dB bandwidths are greater than 650㎒ and the gain errors are less than 0.3dB in a gain control range from -12dB to +12dB in 6dB steps. It consumes 3.1㎃ from a 2.5V supply voltage.

• Journal of IKEEE
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• v.14 no.1
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• pp.65-74
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• 2010

The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a $0.18{\mu}m$ CMOS process. It satisfies the DTV(ATSC) frequency band(54~806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6~3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59~94MHz(${\pm}$17.7MHz/V,${\pm}$23%) and frequency steps of 26~42.5MHz(${\pm}$8.25MHz/V,${\pm}$24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than $10{\mu}$sec. It consumes 20~23mA from a 1.8V supply, and the chip size including PADs is 2.0mm${\times}$1.8mm.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.6
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• pp.80-87
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• 2018

In recent years, due to the spread of various renewable energy power sources and the pursuit of high efficiency and low-power consumption, not only trends in the electric power industry but also the consumption, control methods, and characteristics are diversified. However, in this diversified electric power industry, the fuse (which is the core part responsible for safety) has not developed significantly in classical operation mode, and thus, fires continue to occur. In this paper, the effects of low melting-point metal plating and high melting-point metal plating on operating characteristics and IT curve movement of the fuse are investigated in a cartridge fuse, which is a classic fuse manufacturing method. The effects of plating on the thickness of the fuse are investigated, and various operating characteristics of the fuse are implemented. In addition, it is suggested that the plating of the low melting-point metal moves the rated current line of the fuse to a low rating, and moves operating characteristics to characteristics of delay operation. It is possible to design various operating characteristics using this characteristic.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.61-70
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• 2016

This paper describes a new PMU(parametric measurement unit) design technique for automatic test equipment(ATE). Only one DDA(differential difference amplifier) is used to force the test signals to DUT(device under test), while conventional design uses two or more amplifiers to force test signals. Since the proposed technique does not need extra amplifiers in feedback path, the proposed PMU inherently guarantees stable operation. Moreover, to measure the response signals from DUT, proposed technique also adopted only one DDA amplifier as an IA(instrument amplifier), while conventional IA uses 3 amplifiers and several resistors. The DDA adopted two rail-to-rail differential input stages to handle full-range differential signals. Gain enhancement technique is used in folded-cascode type DDA to get open loop gain of 100 dB. Proposed PMU design enables accurate and stable operation with smaller hardware and lower power consumption. This PMU is implemented with 0.18 um CMOS process and supply voltage is 1.8 V. Input ranges for each force mode are 0.25~1.55 V at voltage force and 0.9~0.935 V at current force mode.