• Journal of IKEEE
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• v.18 no.3
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• pp.335-340
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• 2014

Recently, LED (Light Emitting Diode) becomes to be useful to apply for the lightening sources in electric systems and the lightening equipment since the power is less consumed with high efficiency, and the size and the weight of LED are small and light, respectively. The LED is controlled with constant current and SMPS (Switching Mode Power Supply). It is necessary for the LED manufacturer to secure the fundamental technology of designing LED chip, and to study the methodology to improve the power factor (PF) and to design the operational circuit for the development of LED to reduce the power loss in the application of LED lightening. The direct AC (Alternating Current) LED driving circuit, HV9910, is widely used in the industry field. In this paper, it is to evaluate the improved methodology for the power factor and efficiency through simulations when PFC (Power Factor Correction) and Noise Filter are added to HV9910.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.2
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• pp.207-212
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• 2012

In this work, a 70/140 GHz dual-band push-push voltage controlled oscillator(VCO) has been developed based on a 0.18-${\mu}m$ SiGe BiCMOS technology. The lower band and the upper band oscillation frequency varied from 67.9 GHz to 76.9 GHz and from 134.3 GHz to 154.5 GHz, respectively, with tuning voltage swept from 0.2 to 2 V. The calibrated maximum output power for each band was -0.55 dBm and -15.45 dBm. The VCO draws DC current of 18 mA from 4 V supply.

• Journal of the Korean Society for Railway
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• v.15 no.6
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• pp.597-603
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• 2012

The cases for selecting contact materials of Ag and AgC for Bias Track Relay are the studies and their safety evaluations are proposed in this paper. The welding at the relative low current has occurred in Ag contacts, but the one has not occurred in AgC contacts although the high currents flow since it has an excellent temperature characteristic. In the repetitive switching experiment, more unstable resistance and transfer phenomena has occurred in contacts as the switching numbers of AgC contacts increase, which results in more consumption of contacts. In the experiments, there exists a trade off relationship between welding and resistance variation. AgC contacts have excellent characteristics in welding, but the caution is required in using them since a lot of repetition switching produces much resistance variation. However, Ag contacts have excellent characteristics in repetitive switching, but weak ones in welding.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.7B
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• pp.1081-1090
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• 2010

$0.18{\mu}m$ CMOS UHF RFID tag frontend is presented in this paper. Several key components are highlighted: the voltage multiplier based on the threshold voltage terminated circuit, the demodulator using current mode, and the clock generator. For standard compliance, all designed components are under the EPC Global Class-1 Generation-2 UHF RFID protocol. Backscatter modulation uses the pulse width modulation scheme. Overall performance of the proposed tag chip was verified with the evaluation board. Prototype Tag Chip dimension is neary 0.77mm2 ; According to the simulation results, the reader can successfully interrogate the tag within 1.5m. where the tag consumes the power about $71{\mu}W$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.35-42
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• 2010

This paper describes a 10 bit 80MHz CMOS D/A converter for wireless communication system. The proposed circuit in the paper is implemented with a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process. The architecture of the circuit consists of the 4bit LSB with binary decoder, and both the 3bit ULSB and the 3bit MSB with the thermometer decoder. The measurement results demonstrates SFDR of 60.42dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB of 8.75bit. INL and DNL have been measured to be ${\pm}$0.38LSB and ${\pm}$0.32LSB and glitch energy is measured to be 4.6$pV{\cdot}s$. Total power dissipation is 48mW at 80MHz(maximum sampling frequency) with a single power supply of 1.8V.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.244-250
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• 2012

This paper describes a 4-Gb/s receiver circuit for a low-swing ground-referenced differential signaling system. The receiver employs a common-gate level-shifter and a continuous linear equalizer which compensates inter-symbol-interference (ISI) and improves voltage and timing margins. A bias circuit maintains the bias current of the level-shifter when the common level of the input signal changes. The receiver is implemented with a low-power 65-nm CMOS technology. When 4-Gb/s 400mVp-p signals are transmitted to the receiver through the channel with the attenuation of -19.7dB, the timing margin based on bit error rate (BER) of $10^{-11}$ is 0.48UI and the power consumption is as low as 0.30mW/Gb/s.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.185-194
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• 2014

In this paper, we proposed the clothing management system using the smart hanger. Proposed system consists of smart hanger, base module, and server, and the smart hanger consists of MCU, LED, RFID reader, RF chip, ring sensor, and battery. The smart hanger reads the RFID tag attached to the clothes and wirelessly transmitted to the server. The server associated base module communicates with the smart hanger and transmits information to the server. The server manages clothing through the DB, and can display various information through the web page and the smart phone. In order to verify the usefulness of the proposed system, we did experiment with the management system for clothing store and laundry where using a lot of hangers. Performance tests of the smart hanger are applied to check the current consumption and can be predicted the battery life with the proposed low power algorithm. The clothing store management system can be increased sales and convenience of the consumer. The laundry management system can be increased the efficiency of laundry category and convenience of the consumer.

• Journal of IKEEE
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• v.15 no.1
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• pp.57-63
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• 2011

This paper presents a tunable band pass filter (BPF) for multi bio-signal detection. The bandwidth can be controlled by the bias current of transconductance (gm), while conventional BPF exploited switchable capacitor array for band selection. With this design technique, the die area of proposed BPF reduced to at least one tenth the area of conventional design. The simulation results show the high cut-off frequency tuning range of from 100Hz to 1Khz. The circuit was implemented with a 0.18um CMOS standard technology. Total current consumption is 1uA at the supply voltage of 1V with sub-threshold design technique.

• Journal of IKEEE
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• v.15 no.1
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• pp.29-36
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC is employed to overcome the problems of dithering scheme. A 2.4GHz LC-based DCO has been designed in a $0.13{\mu}m$ CMOS process with an enhanced frequency resolution for wireless local area network applications. It has a frequency tuning range of 900MHz and a resolution of 58.8Hz. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The designed DCO exhibits a phase noise of -123.8dBc/Hz at 1MHz frequency offset. The DCO core consumes 4.2mA from 1.2V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.66-70
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• 2016

This paper presents an 24 GHz I/Q LO generator for a heartbeat measurement radar system. In order to improve the mismatch performance between I and Q LO signals against process variation, a 24 GHz I/Q LO generator employing a low-pass phase shifter and a high-pass phase shifter composed of inductors and capacitors is proposed. The proposed 24 GHz I/Q LO generator consists of an LO buffer, a low-pass phase shifter and a high-pass phase shifter. It was designed using a 65 nm CMOS technology and draws 8 mA from a 1 V supply voltage. The proposed 24 GHz I/Q LO generator shows a gain of 7.5 dB, a noise figure of 2.3 dB, 0.1 dB gain mismatch and $4.3^{\circ}$ phase mismatch between I and Q-path against process and temperature variations for the operating frequencies from 24.05 GHz to 24.25 GHz.