• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.57-63
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• 2014

This paper proposes an architecture of $3^{rd}$ order SDM(Sigma-Delta Modulator) with delayed feed-forward path in order to reduce the power consumption and area. The proposed SDM improve the architecture of conventional $3^{rd}$ order SDM which consists of two integrators. The proposed architecture can increase the coefficient values of first stage doubly by inserting the delayed feed-forward path. Accordingly, compared with the conventional architecture, the capacitor value($C_I$) of first integrator is reduced by half. Thus, because the load capacitance of first integrator became the half of original value, the output current of first op-amp is reduced as 51% and the capacitance area of first integrator is reduced as 48%. Therefore, the proposed method can optimize the power and the area. The proposed architecture in this paper is simulated under conditions which are supply voltage of 1.8V, input signal 1Vpp/1KHz, signal bandwidth of 24KHz and sampling frequency of 2.8224MHz in the 0.18um CMOS process. The simulation results are SNR(Signal to Noise Ratio) of 88.9dB and ENOB(Effective Number of Bits) of 14-bits. The total power consumption of the proposed SDM is $180{\mu}W$.

• Proceedings of the KAIS Fall Conference
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• 2005.05a
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• pp.159-162
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• 2005

전자빔을 이용하던 CRT(Cathode Ray Tube) 모니터에서 픽셀단위의 LCD(Liquid Crystal Display) 디스플레이 사용으로 휴대용 정보처리 장치들은 급속한 발전을 이루게 되었다. 기존의 CRT 모니터에서 전자빔을 사용하던 방식에서 픽셀(Pixel) 단위의 후면발광 디스플레이를 만들면서 CRT 모니터보다 빠른 응답특성을 나타내며 저 전력일 뿐만 아니라 디스플레이의 두께도 줄일 수 있게 되었다. 휴대가 가능한 디스플레이의 발전으로 노트북이나 PDA와 같은 실시간 정보를 활용 및 처리 할 수 있는 방법들을 제시할 수 있었지만 원활한 활용을 위해 더 적은 전력을 사용하는 방법들이 제시되어야 했다. 이에 따라 저 전력 소모, 빠른 응답특성, 넓은 시야각 그리고 경량화가 가능한 디스플레이가 되기 위한 새로운 디스플레이가 선을 보이게 되었다. 현재 차세대 디스플레이로 각광을 받고 있는 디스플레이 소자로는 OLED(Organic Light Emitting Diode)가 있다 이는 LCD 디스플레이가 가지고 있는 단점을 보완하여 우선적으로 높은 색도가 가능하며 후면발광을 사용하지 않고 자체 발광을 하기 때문에 저 전력 소모가 현실화되었다. 또한 디스플레이의 유동성이 가능하여 휘어질 수 있는 특성을 가지고 있다. 그러나 이러한 유기발광 소자의 경우 높은 발광 효율을 위한 구조적 개선이 필요하며 소자의 수명도 개선해야 한다. 이에 따라 유기발광 소자의 메카니즘에 대한 파악이 필요하게 되며 물리적 구조에 대한 이해가 필요하다. 이를 위해 물리적, 수치적 해석으로 소자의 특성을 파악해 줌으로써 개선된 유기발광 소자 제작이 가능 할 것이다.기에 대한 영향정도를 측정하여 정량적으로 도출하였다. 이를 각 구간에 대해 상호 비교 분석함으로써 대형국책사업에서의 공기지연인자에 대한 분석 방법론을 정립하였고 공기지연 분석 방법론의 현실적 적용을 위한 제언과 그에 따른 개선사항에 대해 도출하였다.있는 발판을 마련하게 된다고 추정하였다. 0.5%가 control사이에서 0.95로 가장 색차가 크게 나타났으며, 그 다음이 냉동분쇄 0.5% 0.83으로 나타나 송이의 첨가율이 높을수록 색차가 크게 나타나는 것을 알 수 있다. 색차가 가장 낮은 제품은 법동분쇄 0.3%, 동결건조 0.3%로 나타났다. 송이양갱의 색(color), 냄새(flavor), 맛(taste), 외관(appearances), 질감(viscosity), 종합적 평가(overall acceptability) 등의 관능평가를 실시한 결과 중 색에 대한 기호도는 냉동분쇄 0.1% 송이양갱이 가장 높은 것으로 나타났으나, 집단간 유의한 차이는 나타나지 않았고, 냄새는 동결건조 0.1%의 송이양갱이 3.38로 가장 점수가 높았으며, 냉동분쇄 0.3%의 송이양갱이 2.81로 가장 낮은 기호도를 나타내었다. 맛에서는 p<0.01수준에서 집단간 유의한 차이를 나타내었는데, 동결건조 0.1%가 그 중 가장 높은 기호도를 나타내었으며, 그 다음이 동결건조 0.5%였다. 가장 낮은 선호도를 나타낸 것은 열풍건조 0.5%였다. 질감은 P<.05 수준에서 집단간 유의미한 차이를 나타내었으며 동결건조 0.1%가 가장 높은 기호도를 나타내었으며, 동결건조 0.5%함유 송이양갱이 1.21로서, 현저히 낮은 기호도를 나타내었다. 종합적인 평가에서는 동결건조 0.1%함유

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.47-52
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• 2006

This paper proposes a novel low-power $32bit\times32bit$ multiplier for deep submicron technologies beyond 130nm. As technology becomes small, static power due to leakage current significantly increases, and it becomes comparable to dynamic power. Recently, shutdown method based on MTCMOS is widely used to reduce both dynamic and static power. However, it suffers from severe power line noise when restoring whole large-size functional block. Therefore, the proposed multiplier mitigates this noise by shutting down and waking up sequentially along with pipeline stage. Fabricated chip measurement results in $0.35{\mu}m$ technology and gate-transition-level simulation results in 130nm and 90nm technologies show that it consumes $66{\mu}W,\;13{\mu}W,\;and\;6{\mu}W$ in idle mode, respectively, and it reduces power consumption to $0.04%\sim0.08%$ of active mode. As technology becomes small, power reduction efficiency degrades in the conventional clock gating scheme, but the proposed multiplier does not.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.47-55
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• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.31-38
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• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.38-48
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• 2014

In this paper, a design of Signal Processing Analog Front-End IC for Automotive Piezo-Resistive Type Pressure Sensor is presented. In modern society, as the car turns to go from mechanical to electronic technology, the accuracy and reliability of electronic parts required importantly. In order to improve these points, Programmable Gain Amplifier (PGA) amplifies the received signal in accordance with gain for increasing the accuracy after PRT Sensor is operated to change physical pressure signals to electrical signals. The signal amplified from PGA is processed by Digital blocks like ADC, CMC and DAC. After going through this process, it is possible to determine the electrical signal to physical pressure signal. As processing analog signal to digital signal, reliability and accuracy in Analog Front-End IC is increased. The current consumption of IC is 5.32mA. The die area of the fabricated IC is $1.94mm{\times}1.94mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.27-36
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• 2006

Conventional delay-insensitive (DI) data encodings usually require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, an encoder and a decoder circuits, where N-bit data transfer can be peformed with only N+l wires, are proposed. These circuits are based on a quasi delay-insensitive (QDI) model and designed by using current-mode multiple valued logic (CMMVL). The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25 um CMOS technology. In general, simulation results with wire lengths of 4 mm or larger show that the CMMVL scheme significantly reduces delay-power product ($D{\ast}P$) values of the dual-rail encoding with data rate of 5 MHz or more and the 1-of-4 encoding with data rate of 18 MHz or more. In addition, simulation results using the buffer-inserted dual-rail and 1-of-4 encodings for high performance with the wire length of 10 mm and 32-bit data demonstrate that the proposed CMMVL scheme reduces the D*P values of the dual-rail encoding with data rate of 4 MHz or more and 1-of-4 encoding with data rate of 25 MHz or more by up to $57.7\%\;and\;17.9\%,$ respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.38-44
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• 2007

This paper describes a 12 bit 80MHz CMOS D/A converter for wireless transceiver. Proposed circuit in the paper employes segmented structure which consists of four stage 3bit thermometer decoders. Proposed D/A converter is manufactured 0.35um CMOS n-well digital standard process and measurement results show a ${\pm}1.36SB/{\pm}0.62LSB$ of INL/DNL and $46pV{\cdot}s$ of glitch energy. SNR and SFDR are measured to be 58.5dB and 64.97dB @ Fs=80MHz and Fin=19MHz with a total power consumption of 99mW. Such results proved that our work has low power consumption, high linearity, low glitch and improved dynamic performance. Therefore, our work can be appled to various high speed and high performance circuits.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.184-193
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• 2012

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.