• Proceedings of the Korean Information Science Society Conference
• /
• 2004.10a
• /
• pp.535-537
• /
• 2004

최근의 멀티미디어 시스템 설계 (예: 휴대폰, PDA) 경향에서 전력 소모를 줄이는 연구가 매우 긴요한 상황에, 본 연구는 누설 전류(leakage power)를 줄이는 연산 회로 아키텍쳐 합성 기법을 제안한다. 누설 전류를 줄이기 위한 방법으로 본 연구는 Dual threshold Voltage (Dual-V$_{T}$) 기법을 적용한다. 기존의 연구에서는 회로 설계 단계 중 논리나 트랜지스터 수준에서DUal-V$_{T}$를 적용한 방법과는 달리, 보다 상위 단계인 회로의 아키텍쳐 합성 단계에서의 지연시간 제약 조건을 만족하는 범위에서 최소의 누설전류 소모를 위한 합성 기법을 제안한다 따라서, 지연 시간과 누설전류 간의 Trade-Off를 이용하여 설계 조건에 맞는 융통성 있는 설계 결과를 얻을 수 있는 장점을 제공한다. 본 연구는 케리-세이브 가산기 (Carry-Save Adder) 모듈의 생성 과정에 국한된 합성 알고리즘의 적용을 보이고 있지만, 일반적인 연산 모듈을 사용한 아키텍쳐 설계 과정에서도 본 알고리즘을 쉽게 변형, 적용할 수 있다.

• The KIPS Transactions:PartA
• /
• v.17A no.3
• /
• pp.121-126
• /
• 2010

This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.8
• /
• pp.42-45
• /
• 2002

A low power SDRAM output buffer with reduced power line noise and feedthrough current is presented. In multi I/O SDRAM output buffer, feedthrough current as well as the corresponding power dissipation are reduced utilizing proposed undershoot protection circuits. Ground bounce is minimized by the pull down driver using intelligent feedback scheme. Ground bounce noise is reduced by 66.3% and instantaneous and average power are reduced by 27.5% and 11.4%, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.10
• /
• pp.95-104
• /
• 2004

This paper propose a motion estimator architecture to reduce the power consumption of the most-power-consuming motion estimation method when designing multimedia SoC with deep submicron technologies below 0.13${\mu}{\textrm}{m}$. The proposed architecture considers both dynamic and static power consumption so that it is suitable for large leakage process technologies, while conventional architectures consider only dynamic power consumption. Consequently, it is suitable for mobile information terminals such as mobile videophone where efficient power management is essential. It exploits full search method for simple hardware implementation. It also exploits early break-off method to reduce dynamic power consumption. To reduce static power consumption, megablock shutdown method considering power line noise is also employed. To evaluate the proposed architecture when applied multimedia SoC, system-level control flow and low-power control algorithm are developed and the power consumption was calculated based on thor From the simulation results, power consumption was reduced to about 60%. Considering the line width reduction and increased leakage current due to heat dissipation in chip core, the proposed architecture shows steady power reduction while it goes worse in conventional architectures.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.7
• /
• pp.493-502
• /
• 2001

This paper propose a new built-in current sensor(BICS) for current testing that has some advantages compared with conventional logic testing. The designed BICS detects the fault in circuit under test (CUT) and makes a Pass/Fail signal by comparison between CUT current and duplicated inverter current. The proposed circuit consists of a differential amplifier, a comparator and a inverter. It requires 10 MOSFETs and 3 inverters. Since the designed BICS do not require the extra clock, the added extra pin is only one output pin. The mode selection is not used in this circuit. Therefore we can apply the circuit to on-line testing. The validity and effectiveness are verified through the HSPICE simulation of circuits with defects. When CUT is a 8$\times$8 parallel multiplier, area overhead of the BICS is about 4.34%.

• 전기의세계
• /
• v.9
• /
• pp.1-3
• /
• 1962

본고에서는 앞으로의 주된 연구과제인 원자로 Simulator로 쓰일 Repetitive형 Analog계산기의 multiplier용으로 사용하기 위하여, 간단하면서도 조정이 쉬우며 안정도와 신뢰도가 큰 삼극관을 사용한 Convertor 회로를 택하여 이를 실험 검토하는 한편 출력측의 cathode-follower진공관을 5751로 개변하여 우리 실정에 정합토록하였다. 즉 이렇게 하므로서 불필요한 소모전류를 절약하며 충분히 낮은 출력 impedance을 얻을 수 있고 또한 얻기에 용이하고 염가한 진공관을 사용하면서도 훌륭한 특성을 얻을 수 있다.

• Proceedings of the KIPE Conference
• /
• 2017.07a
• /
• pp.389-390
• /
• 2017

본 논문은 전압형 HVDC 시스템의 기술 동향에 대하여 설명하고 있다. 전압형 HVDC 시스템은 무효전력소모가 있고, 전류형 HVDC 시스템은 무효전력 소모가 없기 때문에 시스템의 구성과 제어에 많은 차이를 보이고 있다. 본 논문은 이러한 현황을 요약 정리한 논문이다.

• Proceedings of the Korean Society of Marine Engineers Conference
• /
• 2006.06a
• /
• pp.301-302
• /
• 2006

초고주파 전력 증폭기의 바이어스 전압을 조절하여 온도 변화에 따른 드레인(Drain) 전류의 변화를 억제하기 위한 저가의 능동 바이어스 모듈을 개발한다. 능동 바이어스 모듈을 5 W급 초고주파 전력증폭기에 적용하였을 경우, $0{\sim}60^{\circ}C$까지의 온도변화에 대하여 소모전류 변화량은 0.1 A 이하로 되어야 한다. 본 기술 개발 대상인 능동 바이어스 모듈의 성능 시험을 위한 대상 전력증폭기는 $2.11{\sim}2.17GHz$ 주파수 대역에서 32 dB 이상의 이득과 ${\pm}0.1\;dB$ 이하의 이득 평탄도, -15 dB 이하의 입.출력 반사손실을 가진다.

• Journal of IKEEE
• /
• v.7 no.2 s.13
• /
• pp.236-244
• /
• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.5
• /
• pp.1-10
• /
• 1999

A low power concumption 2.4 GHz one-chip transceiver MMIC was designed and fabricated using $1.0\mu\textrm{m}$ ion-implantation MESFET process and packaged on a 24 lead SSOP. In the transmitter mode, it revealed conversion gain of 7.5 dB, output IP3 of -3.5 dBm, and noise figure of 3.9 dB at 2.44 GHz with 3.9 mA current consumption. In the receiver mode, it revealed voltage sensitivity of 6.5 mV/$\mu\$W with 2 .0 mA current consumption. Comparing the fabricated MMIC with the results of MMICs reported elsewhere, it was shown that the fabricated MMIC had good performance. The low power consumption 2.4 GHz transceiver MMIC is expected to be used for various applications such as wireless local area networks, wireless local loops and RFID tags in ISM-band.