• Journal of KSNVE
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• v.11 no.1
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• pp.68-75
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• 2001

A method for actively controlling dynamic reaction forces in flexible structures subject to persistent excitations is presented. Since reaction forces are not directly measured in flexible structures, reaction forces are estimated by using the Kalman filter. The estimated reaction force is used as an error signal in the adaptive feedforward disturbance cancellation controller. In order to compensate the static effect of the truncated modes in the reaction forces, the residual flexibility matrix is used with the Kalman filter. The paper presents the formulation of the reaction forces in conjunction with the Kalman filter estimator and the adaptive feedforward controller. The results show that the dynamic reaction forces at its supports in a flexible beam test rir are well suppressed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.4
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• pp.582-593
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• 1999

This paper presents the design and fabrication of the diplexer for a KOREASAT-III Ka-band satellite transponder. The transmission characteristics of the diplexer is analyzed by calculating the generalized scattering matrix using mode matching method. It is composed of 2 bandpass filters, coupled with H-plane T-junction having symmetrical inductive iris and E-plane metal insert structures. Compared with the size and weight of the Rx and Tx filter loaded with a transponders respectively, those of the diplexer can be effectively reduced. In a high power transmission, the variation of the filter characteristics is minimized by the scheme that irises are extended to the exterior of H-plane of the waveguide. This scheme needs no extra heat sinks for dissipating high power. The diplexer is designed to improve the simplification, durability and reliability by eliminating tuning screws, which have been used to compensate for the characteristics of fabricated filters. The bandpass filters of the diplexer show the insertion loss of less than 1.2 dB and the return loss in excess of 15 dB. The isolations of more than 65 dB have been achieved between Rx and Tx filter.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.8
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• pp.36-44
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• 1999

This paper presents the design and fabrication of the duplexer for a Ka-band satellite transponder which is analyzed transmission characteristics by calculating the generalized scattering matrix using mode matching method. It is composed of 2 bandpass filters, coupled with H-plane T-junction having symmetrical inductive iris and E-plane metal insert structures. Compared with the size and weight of the Rx and Tx filter loaded with a transponders respectively, those of the duplexer can be effectively reduced. In a high power transmission, the variation of the filter characteristics is minimized by the scheme that irises are extended to the exterior of H-plane of the waveguide. This scheme needs no extra heat sinks for dissipating high power. The duplexer is designed to improve the simplification, durability and reliability by eliminating tuning screws, which have been used to compensate for the characteristics of fabricated filters. The bandpass filters of the duplexer show the insertion loss of less than 1.2 dB and the return loss in excess of 15 dB. The isolations of more than 65 dB have been achieved between Rx and Tx filter.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.2
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• pp.927-939
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• 2015

It appears that the rapid advance in technology has allowed to broaden the variety of rail systems technology, thereby fostering new business opportunity in rail industry. The direction of rail systems operations is mainly two fold. In one direction, long distance operations between mega cities are pursued with help of high speed trains under development. In the other case, relatively short distance operations for covering intra-city or suburban area are becoming popular. A good example of the latter case is light rail transit (LRT) systems. Due to the short distance operation, it is thus expected that both the development and operation cost for LRT systems be reduced to some extent. The cost reduction desired in there can be gained by scaling down the sizes of both the trains and stations as compared to those of normal rail systems. However, it is not well known how the LRT stations can be scaled down. The objective of this paper is to study on how to slim down the stations (particularly, the functions room) of LRT systems. To achieve the objective, an approach is studied based on a modified method of design structure matrix (DSM). Specifically, using the enhanced DSM method, an integrated architecture is developed for the functions room, in which equipments are housed to perform the functions of electricity, signaling, and communication for LRT stations. The use of the result indicates that the desired reduction can be obtained with the approach taken in the paper.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.201-208
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• 2014

In this paper, we propose the classifier structure design algorithm using DTW. Proposed algorithm uses DTW result to design the binary tree architecture based on the SVM which classify the multi-class data. Design the binary tree architecture for Support Vector Machine(SVM-BTA) using the threshold criterion calculated by the sum columns in square matrix which components are the reference data from each class. For comparison the performance of the proposed algorithm, compare the results of classifiers which binary tree structure are designed based on database and k-means algorithm. The data used for classification is 333 signals from 18 classes of underwater transient noise. The proposed classifier has been improved classification performance compared with classifier designed by database system, and probability of detection for non-biological transient signal has improved compare with classifiers using k-means algorithm. The proposed SVM-BTA classified 68.77% of biological sound(BO), 92.86% chain(CHAN) the mechanical sound, and 100% of the 6 kinds of the other classes.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.18 no.2
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• pp.169-179
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• 2005

An improved method for evaluating effective buckling lengths of beam-column members in plane frames is newly proposed based on system inelastic buckling analysis. To this end, the tangent stiffness matrix of be am-column elements is first calculated using stability functions and then the inelastic buckling analysis method is presented. The scheme for determining effective length of individual members is also addressed. Design examples and numerical results ?uc presented to show the validity of the proposed method.

• Korean Journal of Optics and Photonics
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• v.6 no.4
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• pp.302-309
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• 1995

We desinged a lattice-matched InGaAs/lnGaAsP quantum well laser that lases at $1.55{\mu}m$ at room temperature, and calculated the gain spectrum as a function of injected carrier density and temperature. For the calculation of band structures and momentum matrix elements, we used a transfer JIlatrix method based on a block-diagonalized 8x8 second-order Ii$.$ P Hamiltonian. This lattice-matched quantum well lases in transverse electric mode. As the temperature increases, the lasing wavelength gets longer, the transparency carrier density increases, and the differential gain is reduced. The temperature dependence of the gain spectrum comes from the temperature dependence of the band structure and that of the Fermi function, and the latter contributes dominantly.nantly.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.05c
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• pp.1519-1522
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• 2003

기존의 웹 문서나 컨텐츠들의 표현적 한계를 극복하기 위한 방안으로 메타 데이터에 관한 다양한 연구가 수행되어졌고 그 결과의 산물중에 가장 대표적인 것으로 XML을 들 수 있다. XML은 문서의 내용뿐 아니라 구조까지도 기술할 수 있는 장점을 통해 향후 정보 교환에 핵심적인 역할을 할 것으로 기대되어지고 있으며 이에 따라 XML 문서를 효율적으로 저장하고 검색하기 위한 다양한 연구가 진행되고 있다. BitCube는 Bit-wise 연산이 가능한 3차원 비트맵 인덱싱을 사용하여 XML 문서들의 구조적 유사성에 따라 클러스터링하고 사용자의 질의에 대한 처리를 수행하는 인덱싱 기법으로 그것의 빠른 성능을 입증하였다. 그러나 BitCube의 클러스터링은 XML 문서의 경로에 중점을 둔 것이므로 클러스터와 경로가 담고 있는 실제 단어들간에는 연관성이 없으므로 3차원 비트맵 인덱스는 하나의 평면을 제외한 모든 평면이 굉장히 높은 공간 사용량을 갖는 회소행렬이 된다. 본 논문에서는 늘어나는 방대한 문서의 양으로 인한 시스템의 성능 저하를 막고 안정적인 성능을 유지할 수 있도록 기존 연산의 성능을 저하시키지 않으면서 공간을 최소화 할 수 있는 연결 리스트틀 설계하고 3차원 비트맵 인덱스를 연결 리스트로 재구성하는 방법을 제시한다.

• The Magazine of the IEIE
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• v.11 no.5
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• pp.42-50
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• 1984

국내의 다음세대 컴퓨터 개발을 위한 VLSI 설계와 CAD 분야에 대한 연구 방향을 제시한다. 연구의 목표는 국제적으로 경쟁할 수 있는 VLSI 설계능력과 백만개 정도의 트랜지스터로 자성된 회로를 경제적으로 설계하기 위한 CAD 기술과 System의 확립이다. ·새로운 회로 구조와 알고리즘에 대한 연구 · CAD 도구와 언어의 개발에 관한 첨단 CAD 기술개발연구 · VLSI 설계에 필요한 CAD 도구 이용과 개발에 필요한 표준 인터페이스, 네트워킹, 컴퓨팅 하드웨어. 시스템 소프트웨어에 대한 연구등의 부분으로 크게 나눌 수 있다. 이용 가능한 CAD system을 평가하고 개선하며 첨단 CAD에 대한 소프트웨어와 하드웨어에 대해 · 컴퓨팅 하드웨어 · 프로그램 분위기 · 네트워킹 능력 ·자료 교환을 위한 표준인터페이스 등에 관해 조사분석도 병행한다. CAD에 관한 세부적인 연구 과제는 · 시스템 사양언어 · 설계 검증 ·시스템시뮬레이션· 설계 합성 · 설계 해석· 설계 방법론·디바이스와 공정 모델링 프로그램 등이다. 고속 계산용 VLSI에 관한 구조와 알고리즘은 행렬 계산을 위한 ·분산 배열 처리 회로 ·시스토릭 (Systolic) 배열 회로 ·셀률라(Cellular) 논리 회로 · 3차원 배열 회로 와 · 비규칙적 계산 알고리즘을 갖는 VLSI가 있다. VLSI설계훈련과 CAD 기술 축적을 위해 CAD enter를 설립하여 전국적인 CAD 네트워킹을 관계 연구소와 여러 대학에 가설하며, MPC 계획을 추진한다. VLSI설계 가능성이 입증되면 VLSI 설계능력을 더욱 향상 시키기 위해 0.5∼1.0mm기술의 silicon faundary를 설립한다. 연구 개발 조직은 대학, 산업체. 연구소가 삼위일체가 되어 수행될 수 있도록 연구 개발 위원회를 설치 운영하며 경쟁적이며 경제적으로 연구 업무를 집행하는 것이 바람직하다.았다.형질에 관여하는 귀전자에 미치는 기구에 대하여 검토할 여타가 있다고 보여진다. 분해능의 특징으로 미루어 앞으로는 레이저를 이용한 계측 방법이 그 주류를 이룰 것으로 사료된다. 우선 본 해설은 기체의 온도 및 농도의 광학적 측정방법중 Raman산란광 검출법에 대하여 실제로 측정하는 입장에서 간단히 소개한다.lity)이, 높은 $GA_3$함량에 기인된다'는 주장은 본실험(本實驗)으로 부인(否認)되었다. 따라서, 응용학적(應用學的) 측면에서 고려해 볼 때, 리베스식물(植物)의 육종기간 단축을 위한 모든 화아분화(花芽分化) 촉진 조치는 P.J.-식물(植物)이 20. node이상 생육하였을 때 취하는 것이 효율적인 것으로 결론 지어진다.앞당겨진 7月 셋째 週였다. 8. Culex (Culex) tritaeniorhynchus summoro년의 最大發生 peak는 1981年, 1982年 모두 8月 둘째 週였다. 9. Anopheles (Anopheles) sinensis의 最大發生 peak는 1981年에 7月 다섯째 週, 1982年은 2週 앞당겨진 7月 셋째 週였다. 10. 重要 3種의 最大 peak를 比城하면 Culex (Culex) pipiens pallens와 Anopheles (Anopheles) sinensis는 1981年과 1982年 모두 最大 peak時期가 同一하였으며, Culex (Culex) tritaeniorhynchus summoro년는 2年間 모두 8月둘째 週에 나타났다.osterior to manubrium and anterior to aortic arch) replacing the normal mediastinal fat. (2) In benign thymoma, the marging of the mass was smooth and the normal fat

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.31-40
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• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.