• Title/Summary/Keyword: 상시불통

Search Result 3, Processing Time 0.017 seconds

Reliability Assessment of Normally-off p-AlGaN-gate GaN HEMTs with Gate-bias Stress (상시불통형 p-AlGaN-게이트 질화갈륨 이종접합 트랜지스터의 게이트 전압 열화 시험)

  • Keum, Dongmin;Kim, Hyungtak
    • Journal of IKEEE
    • /
    • v.22 no.1
    • /
    • pp.205-208
    • /
    • 2018
  • In this work, we performed reverse- and forward-gate bias stress tests on normally-off AlGaN/GaN high electron mobility transistors(HEMTs) with p-AlGaN-gate for reliability assessment. Inverse piezoelectric effect, commonly observed in Schottky-gate AlGaN/GaN HEMTs during reverse bias stress, was not observed in p-AlGaN-gate AlGaN/GaN HEMTs. Forward gate bias stress tests revealed distinct degradation of p-AlGaN-gate devices exhibiting sudden increase of gate leakage current. We suggest that forward gate bias stress tests should be performed to define the failure criteria and assess the reliability of normally off p-AlGaN-gate GaN HEMTs.

Design of Normally-Off AlGaN Heterojunction Field Effect Transistor Based on Polarization Engineering (분극 엔지니어링을 통한 상시불통형 질화알루미늄갈륨 이종접합 전계효과 트랜지스터 설계)

  • Cha, Ho-Young;Sung, Hyuk-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.16 no.12
    • /
    • pp.2741-2746
    • /
    • 2012
  • In this study, we propose a novel structure based on AlGaN substrate or buffer layer to implement a normally-off mode transistor that was difficult to be realized by conventional AlGaN/GaN heterojunction structures. The channel under the gate can be selectively depleted by growing an upper AlGaN barrier with a higher Al mole fraction and a top GaN charge elimination layer on AlGaN substrate or buffer layer. The proposed AlGaN heterojunction field effect transistor can achieve a threshold voltage of > 2 V, which is generally required in power device specification.

Gate Field Alleviation by graded gate-doping in Normally-off p-GaN/AlGaN/GaN Hetrojunction FETs (상시불통형 p-GaN/AlGaN/GaN 이종접합 트랜지스터의 게이트막 농도 계조화 효과)

  • Cho, Seong-In;Kim, Hyungtak
    • Journal of IKEEE
    • /
    • v.24 no.4
    • /
    • pp.1167-1171
    • /
    • 2020
  • In this work, we proposed a graded gate-doping structure to alleviate an electric field in p-GaN gate layer in order to improve the reliability of normally-off GaN power devices. In a TCAD simulation by Silvaco Atlas, a distribution of the graded p-type doping concentration was optimized to have a threshold voltage and an output current characteristics as same as the reference device with a uniform p-type gate doping. The reduction of an maximum electric field in p-GaN gate layer was observed and it suggests that the gate reliability of p-GaN gate HFETs can be improved.