• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1163-1170
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.397-409
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• 2003

This paper describes an implementation of radix-4 trellis parallel architecture and backward state transition control trace back Viterbi decoder, and presents the application results to high speed wireless LAN. The radix-4 parallelized architecture Vietrbi decoder can not only improve the throughput with simple structure, but also have small processing delay time and overhead circuit compared to M-step trellis architecture one. Based on these features, this paper addresses a novel Viterbi decoder which is composed of branch metric computation, architecture of ACS and trace back decoding by sequential control of backward state transition for the implementation of radix-4 trellis parallelized structure. With the proposed architecture, the decoding of variable code rate due to puncturing the base code can easily be implemented by the unified Viterbi decoder. Moreover, any additional circuit and/or peripheral control logic are not required in the proposed decoder architecture. The trace back decoding scheme with backward state transition control can carry out the sequential decoding according to ACS cycle clock without additional circuit for survivor memory control. In order to evaluate the usefulness, the proposed method is applied to channel CODEC of the IEEE 802.11a high speed wireless LAN, and HDL coding simulation results are presented.

• Bulletin of the Society of Naval Architects of Korea
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• v.54 no.4
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• pp.39-46
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• 2017

Jack-up drilling rigs are widely used in offshore oil and gas exploration industry. It is originally designed for use in the shallow waters less than 60m of water depth; there is growing demand for their use in deeper water depth over 150m and harsher environmental conditions. In this study, global in-place analysis of jack-up rig leg for North-sea oil well is performed through numerical analysis. Firstly, environmental conditions and seabed characteristics at the North-sea are collected and investigated measurements from survey report. Based on these data, design specifications are established and the overall basic design is performed. Dynamic characteristics of the jack-up rig for North-sea are considered in the global in-place analysis both leg and hull and the basic stability against overturning moment is also analyzed. The structural integrity of the jack-up rig leg/hull is verified through the code checks and the adequate safety margin is observed. The uncertainty in jack-up behaviour is greatly influenced by the uncertainties in the soil characteristics that determine the resistance of the foundation to the forces imposed by the jack-up structure. Among the risks above mentioned, the punch-through during pre-loading is the most frequently encountered foundation problem for jack-up rigs. The objective of this paper is to clarify the detailed structure and installation engineering matters for prove the structural safety of jack-up rigs during operation. With this intention the following items are addressed; - Characteristics of structural behavior considering soil effect against environmental loads - Modes of failure and related pre-loading procedure and parameters - Typical results of structural engineering and verification by actual measurement.

• Journal of the Korean Recycled Construction Resources Institute
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• v.4 no.4
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• pp.99-104
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• 2009

For recycling of waste foundry sands, researchers recently try to recycle them rather than depend on reclamation, and are studying on how to combine waste foundry sands with cement and use them for various kinds of construction material as the effective recycling method of waste foundry sand. In this research, The ways to find the proper replacement rate of waste foundry sands and to make use of them were suggested through the experiments on the range to apply waste foundry sands with two levels of 1:3 mixture rate of W/C 43% and 50%. The research result showed that in terms of liquidity as the characteristic of unhardened mortar, as the replacement rate of waste foundry sands increased, its flow tended to decrease. The amount of air also displayed a similar tendency to that of liquidity in that the higher the replacement rate of waste foundry sands became, the lower it became. With regard to the solidity trait of hardened mortar, it increased when the waste foundry sands were replaced more, and the replacement of waste foundry sands caused increased initial solidity. As for the amount of water permeated and that of water absorbed as the water tight proofing properties, the amount of permeated water was proved to decrease because of the gap recharge effect by the fine powder of waste foundry sands, and the replacement of waste foundry sands in the structures requiring watertightness is concluded to be very effective.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.41 no.7
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• pp.635-643
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• 2017

The purpose of this study is to investigate the influence of the cold reduction rate and an ultrasonic fatigue test (UFT) on the fatigue behaviors of STS 304L. The tensile strength, yield strength, hardness value and fatigue limit in the UFT fatigue test linearly increased as thickness decreased from 1.5 mm to 1.1 mm, as the cold reduction rate of STS 304L increased. As a result of the UFT fatigue test (R = -1) of four specimens, the fatigue limit of the S-N curve formed a knee point in the region of $10^6$, and the 2nd fatigue limit caused by giga cycle fatigue did not appeared. In the case of t = 1.1 mm, the highest fatigue limit was 345 MPa, which was 64.3% higher than the original material (t = 1.5 mm). As a result of the UFT fatigue test of STS 304L, many small surface cracks occurred, grown, coalesced while tearing.

• Korean Journal of Materials Research
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• v.11 no.5
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• pp.339-344
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• 2001

An all solid-state thin film supercapacitor (TFSC) with Co$_3$O$_4$/LiPON/Co$_3$O$_4$ structure was fabricated on Pt/Ti/Si substrate using Co$_3$O$_4$ thin film electrode. Each Co$_3$O$_4$ film was grown by reactive dc reactive magnetron sputtering with increasing $O_2$/[Ar+O$_2$] ratio. Amorphous LiPON electrolyte film was deposited on Co$_3$O$_4$/Pt/Ti/Si in pure nitrogen ambient by using reactive rf magnetron sputtering. The electrochemical behavior of the Co$_3$O$_4$/LiPON/Co$_3$O$_4$ multi-layer structures exhibits a behavior of a bulk-type supercapacitor, even though much lower capacity (from 5 to 25 mF/$\textrm{cm}^2$-$\mu\textrm{m}$) than that of the bulk one. It was found that the TFSC showed a fairly constant discharge capacity with a constant current of 50 $\mu\textrm{A}/\textrm{cm}^2$ at the cut-off voltage 0-2V during 400 cycles. It is shown that the electrochemical behavior of the Co$_3$O$_4$/LiPON/Co$_3$O$_4$ TFSC is dependent upon the sputtering gas ratio. The capacity dependency of electrode films on different gas ratios was explained by different structural, electrical, and surfacical properties.

• Journal of the Korean Recycled Construction Resources Institute
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• v.6 no.1
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• pp.88-94
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• 2011

To make recycling aggregate, quantity of fine particles increase due to multi-crushing. Though this particles were mixed with recycling aggregate, those have to be disparted from aggregate in the high quality recycling aggregate, because of the cause of low quality. Considering reactivity, fine particles is better than coarse one. Therefore, it needs to develop suitable usage. We try to make cement extruding material by using the fine particles from concrete recycling, as a silicious replacement. Test results are as follows ; 1) Waste concrete powder has major ingredients such as $SiO_2$ and CaO, its density is $2.45g/cm^3$ being similar to silica powder, its diameter is range 13 to $141{\mu}m$. 2) Considering to strength properties according to particle size, specimen was made using small particles is higher strength than large one. 3) Despite of exception in the autoclaved curing, when the replacement of waste fine particle increase, strength of extruding panel shows almost same level.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.401-404
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• 2015

This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.875-878
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• 2015

In this paper, we propose an intra prediction hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC encoder. The proposed intra prediction hardware architecture uses common operation units to reduce computational complexity and uses $4{\times}4$ block unit to reduce hardware area. In order to reduce operation time, common operation unit uses one operation unit to generate predicted pixels and filtered pixels in all prediction modes. Intra prediction hardware architecture introduces the $4{\times}4$ PU design processing to reduce the hardware area and uses intemal registers to support $32{\times}32$ PU processmg. The proposed hardware architecture uses ten common operation units which can reduce execution cycles of intra prediction. The proposed Intra prediction hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 41.5k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 150MHz, it can support 4K UHD video encoding at 30fps in real time, and operates at a maximum of 200MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.554-557
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• 2016

Recently, supercomputer has been increasingly adopted as a computing environment for scientific simulation as well as education, healthcare and national defence. Especially, supercomputing system with heterogeneous computing resources is gaining resurgence of interest as a next-generation problem solving environment, allowing theoretical and/or experimental research in various fields to be free of time and spatial limits. However, traditional supercomputing services have only been handled through a simple form of command-line based console, which leads to the critical limit of accessibility and usability of heterogeneous computing resources. To address this problem, in this paper, we provide the design and implementation of web-based HPC (High Performance Computing) job management framework for computational scientific simulation. The proposed framework has highly extensible design principles, providing the abstraction interfaces of job scheduler (as well as bundle scheduler plug-ins for LoadLeveler, Sun Grid Engine, OpenPBS scheduler) in order to easily incorporate the broad spectrum of heterogeneous computing resources such as cluster, computing cloud and grid. We also present the detailed specification of HTTP standard based RESTful endpoints, which manage simulation job's life-cycles such as job creation, submission, control and status monitoring, etc., enabling various 3rd-party applications to be newly created on top of the proposed framework.