• Journal of the Korea Society of Computer and Information
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• v.10 no.6 s.38
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• pp.227-232
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• 2005

A network of Packet based switch Mode will be required to carry the traffics(CVR,VBR, UBR, ABR) generated by a wide range of services. Packet based Network services the quality-of-Service (QoS) management of traffic sources and bandwidth. Besides efficiency and throughput services are achieved in the multimedia traffic sent in the network. In this paper. the scheduler transmits the safe packet, drop the unsafe packet and evaluate unsafe packet as the requirement of the delay avoiding the network congestion for improving the QoS of the multimedia network In this paper. we Propose the scheduling algorithm which evaluates and drops the packet . The suggested model performance of the switch is estimated and simulated in terms of the delay by computer.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.84-92
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• 2007

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller and simplifies the test procedure and reduces the area overhead.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.727-729
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• 2005

현재 3차원 그래픽 가속기에서 성능 향상에 대한 문제점으로 대두되고 있는 것은 실제 화면에 그려지는 정보가 저장되는 프레임버퍼에 대한 접근 지연이다. 따라서 본 논문은 기존 픽셀 캐쉬가 포함된 래스터라이져 구조에서 캐쉬 읽기 접근 실패 시 발생하는 패널티와 이에 따른 프레임버퍼에 대한 지연이 발생하는 문제점을 개선하고자, 기존 래스터라이져를 래스터라이져와 합성기로 구분하고 그 사이에 캐쉬 읽기 접근 실패 시 프레임 버퍼에서 정보를 읽어오지 않는 깊이 캐쉬와 색상 캐쉬가 쌍을 이룬 픽셀 캐쉬 메모리 시스템으로 구성된 개선된 3차원 그래픽 가속기 구조을 제안하고 실험을 수행하였다. 실험 결과 제안하는 3차원 그래픽 가속기 구조가 기존 구조에 비해 캐쉬 접근 실패율이 약 $23\%$ 감소하였으며, 평균 메모리 접근 사이클이 $10\%-13\%$ 감소하였으며 이는 상당수의 프레임버퍼에 대한 접근 지연을 감소시킨 것이다. 합성기와 메모리 간의 대역폭은 약 $10\%$ 증가하지만 파이프라인의 작업에는 영향을 미치지는 않는다.

• Journal of Korea Multimedia Society
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• v.12 no.2
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• pp.165-177
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• 2009

Embedded database systems (EDBMS) based on NAND flash memories are widely adopted for logging data on sensor nodes. Since write and erase operations of a flash memory are time consuming compared to read operations and wear memory cells, it is important to reduce these operations to enhance the EDBMS performance and to extend the memory life. In this paper, we propose a delayed write scheme to archive this goal. Proposed scheme stores updated parts of database pages into delayed write records to reduce the database page writes. By doing that, it decreases write and erase operations on a flash memory. Therefore, the proposed scheme enhances the logging performance of a write-intensive EDBMS on a sensor node and extends the flash memory life.

• Journal of the Korea Society of Computer and Information
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• v.10 no.5 s.37
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• pp.245-250
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• 2005

A network of Packet based switch Mode will be required to carry the traffics(CVR,VBR, UBR, ABR) generated by a wide range of services. Packet based Network services the Qualify-of-Service (QoS) management of traffic sources and bandwidth. Besides efficiency and throughput services are achieved in the multimedia traffic sent in the network. In this paper, the scheduler transmits the safe packet, drop the unsafe packet and evaluate unsafe Packet as the requirement of the delay avoiding the network congestion for improving the QoS of the multimedia network. In this paper, we Propose the scheduling algorithm which evaluates and drops the packet The suggested model Performance of the switch is estimated and simulated in terms of the delay by computer.

• 한국HCI학회:학술대회논문집
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• 2007.02a
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• pp.64-69
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• 2007

이 논문은 촉각 가상 환경(Haptic Virtual Environment)에서 촉각(haptic) 데이터를 촉각 데이터 특성에 맞추어 네트워크에 적응적이고 효율적으로 전송할 수 있는 전송 알고리즘을 제안한다. 촉감 상호작용 측정을 위해 네트워크 햅틱 협업 응용을 작성하였고 지연, 지터, 손실에 따른 변화를 분석하였다. 이를 바탕으로 네트워크 트래픽에 적응할 수 있는 알고리즘을 구성하였다. 손실되거나 지터의 영향을 받은 패킷에는 간단한 선형예측 방법을 사용하여 보상하여 손실과 지터로 인한 오차를 줄였다. 이는 심각한 손실이나 지터에 의해 떨림 현상이 나타나는 햅틱 장치의 문제점을 개선하게 되었다. 또한 네트워크 협업에서 지연이 발생할 때 나타나는 클라이언트들 사이의 비동시성을 해결하기 위하여 완충시간을 두었다. 지연이 큰 클라이언트는 버퍼를 사용하지 않고 실시간으로 처리하고, 지연이 적은 클라이언트는 버퍼를 사용하여 전송받은 좌표를 완충시킨 후에 처리하는 방법을 사용하여 클라이언트들 사이의 햅틱 렌더링을 동기화 하였다. 제안된 알고리즘은 다양한 네트워크 상황에서의 협업에서 개선된 결과를 보였다. 이를 바탕으로 향후 선형예측 방법을 다양하게 적용시키고 서버와 클라이언트 사이의 동기화를 구현하는 알고리즘을 작성할 것이다. 본 논문은 다양한 네트워크 상황 에서 햅틱 데이터를 전송하고 처리하는 연구의 기초자료가 될 수 있을 것이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.2
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• pp.417-426
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• 2000

In this paper, CE-CPSK(Constant Envelope Continuous Phase Shift Keying) modulated DS/SS(Direct Sequence Spread Spectrum) transceiver with 908 MHz carrier frequency and 1.5 MHz PN clock rate is proposed. To overcome the effect of nun-linear power amplifier, CE-CPSK modulation method which has the constant envelope and continuous phase characteristics is proposed. To analyze the DS/SS receiver performance with respect to code tracking loop, multipath fading channel is characterized as a two-ray Rayleigh fading channel. To compensate the demerit of analog delay locked loop, digital delay locked loop is employed for code tracking loop. Simulation and experimental examination has been carried out in AWGN(Additive White Gaussian Noise) and Rayleigh fading channel environment in order to prove validity of the proposed method.

• Journal of the Korea Society of Computer and Information
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• v.9 no.4 s.32
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• pp.173-178
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• 2004

A network of Asynchronous Transfer Mode (ATM) will be required to carry the traffics(CVR, VBR, UBR. ABR) generated by a wide range of services ATM services the Quality-of-Service (QoS) management of traffice sources and bandwidth. Besides efficiency and throughput, the security services are achieved in the traffic sent in ATM network. In this paper, the scheduler evaluate and the packets sent in ATM security group. The scheduler transmits the safty packet, drop the unsafty packet and evaluate mark packet as the requirement of the delay. In this paper, we propose the scheduling algorithm of mark packet which evaluates the packet. The suggested model performance of the firewall switch is estimate simulation in terms of the delay by computer.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.245-251
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• 2016

This paper suggests a heuristic algorithm to obtain optimal solution of minimum number of aircraft delay in multi-airport arrivals/departures problem. This single airport arrivals/departures problem can be solved by mathematical optimization method only. The linear programming or genetic algorithm that is a kind of metaheuristic method is used for a multi-airport arrivals/departures problem. Firstly, the proposed algorithm selects the median minimum delays capacity in various arrivals/departures capacities at an airport for the number of aircraft in $i^{th}$ time interval (15 minutes) at each airport. Next, we suggest reallocate method for arrival aircraft between airports. This algorithm better result of the number of delayed aircraft then genetic algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.67-74
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• 2000

In this paper, a $54{\times}54$-bit multiplier based on a improved conditional sum adder is proposed. To reduce the multiplication time, high compression-rate compressors without Booth's Encoding, and a 108-bit conditional sum adder with separated carry generation block, are developed. Furthermore, a design technique based on pass-transistor logic is utilized for optimize the multiplication time and the power consumption by about 5% compared to that of conventional one. With $0.65{\mu}m$, single-poly, triple-metal CMOS process, its chip size is $6.60{\times}6.69\;mm^2$ and the multiplication time is 135.ns at a 3.3V power supply.