• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.11C
• /
• pp.1077-1087
• /
• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.11
• /
• pp.14-23
• /
• 2002

Two implementation methods for SOVA (Soft Output Viterbi Algorithm)of Turbo decoder are applied and verfied. The first method is the combination of a trace back (TB) logic for the survivor state and a double trace back logic for the weight value in two-step SOVA. This architecure of two-setp SOVA decoder allows important savings in area and high-speed processing compared with that of one-step SOVA decoding using register exchange (RE) or trace-back (TB) method. Second method is adjusting the reliability value with a scaling factor between 0.25 and 0.33 in order to compensate for the distortion for a rate 1/3 and 8-state SOVA decoder with a 256-bit frame size. The proposed schemes contributed to higher SNR performance by 2dB at the BER 10E-4 than that of SOVA decoder without a scaling factor. In order to verify the suggested schemes, the SOVA decoder is testd using Xillinx XCV 1000E FPGA, which runs at 33.6MHz of the maximum speed with 845 latencies and it features 175K gates in the case of 256-bit frame size.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.2
• /
• pp.7-13
• /
• 2011

This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.5 s.335
• /
• pp.55-62
• /
• 2005

In this paper, we propose an efficient symbol detection algorithm for space-frequency OFDM (SF-OFDM) transmit diversity scheme and present the implementation results of the SF-OFDM WLAN baseband processor with the proposed algorithm. When the number of sub-carriers in SF-OFDM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithm eliminates this interference in a parallel manner and obtains a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithm obtains about 3 dB gain over the conventional detection algorithm. The packet error rate (PER), link throughput, and coverage performance of the SF-OFDM WLAN with the proposed detection algorithm are also estimated. For the target throughput at $80\%$ of the peak data rate, the SF-OFDM WLAN achieves the average SNR gain of about 5.95 dB and the average coverage gain of 3.98 meter. The SF-OFDM WLAN baseband processor with the proposed algorithm was designed in a hardware description language and synthesized to gate-level circuits using 0.18um 1.8V CMOS standard cell library. With the division-free architecture, the total logic gate count for the processor is 945K. The real-time operation is verified and evaluated using a FPGA test system.

• Journal of Broadcast Engineering
• /
• v.16 no.6
• /
• pp.986-995
• /
• 2011

In this paper, we propose a noise whitening decision feedback equalizer for single carrier frequency division multiple access (SC-FDMA) receivers. SC-FDMA has the same advantage as that of orthogonal frequency division multiple access (OFDMA) in which the multipath effect can be removed easily, and also solves the problem of high peak to average power ratio (PAPR) which is the main drawback of OFDMA. Although SC-FDMA is a single carrier transmission scheme, a simple frequency domain linear equalizer (FD-LE) can be implemented as in OFDMA, which can dramatically reduce the equalizer complexity. Moreover, some residual intersymbol interference in the output of the FD-LE can be further removed by an additional nonlinear decision feedback equalizer (DFE) in time domain, because the time domain signal is a digitally modulated symbol. In the conventional DFE, however, the noise is not white at the input of the decision device and correspondingly the decision is not optimum. In this paper, we propose an improved DFE scheme for SC-FDMA systems where a linear noise whitening filter is inserted before the decision device of the conventional DFE scheme. Through computer simulations, we compare the bit error rate performance of the proposed DFE scheme with the conventional equalizers.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.5
• /
• pp.902-910
• /
• 2016

Recently, the volume of mobile data traffic increases exponentially due to the emergence of various mobile services. In order to resolve the problem of mobile traffic increase, various new technologies have been devised. Especially, two-way relay communication in which two nodes can transfer data simultaneously through relay node, has gained lots of interests due to its capability to improve spectral efficiency. In this paper, we analyze the SM-PNC which combines Physical-layer Network Coding (PNC) and Spatial Modulation (SM) under two-way relay communication environment. Log-Likelihood Ratio (LLR) is considered and both separate decoding and direct decoding have been taken into account in performance analysis. Through performance evaluation, we have found that the bit error rate of the proposed scheme is improved compared to that of the conventional PNC scheme, especially when SNR is high and the number of antennas is large.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.7
• /
• pp.53-60
• /
• 2009

Motion estimation for H.264/AVC video CODEC is very complex and requires a huge amount of computational efforts because it uses multiple reference frames and variable block sizes. We propose the architecture of high-performance integer-pixel motion estimation circuit based on fast algorithms for multiple reference frame selection, block matching, block mode decision and motion vector estimation. We also propose the architecture of high-performance interpolation circuit for sub-pixel motion estimation. We described the RTL circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The integer-pixel motion estimation circuit consists of 77,600 logic gates and four $32\times8\times32$-bit dual-port SRAM's. It has tile maximum operating frequency of 161MHz and can process up to 51 D1 (720$\times$480) color in go frames per second. The fractional motion estimation circuit consists of 22,478 logic gates. It has the maximum operating frequency of 200MHz and can process up to 69 1080HD (1,920$\times$1,088) color image frames per second.

• The Journal of the Acoustical Society of Korea
• /
• v.19 no.1
• /
• pp.97-102
• /
• 2000

Subband coding is to divide the signal frequency band into a set of uncorrelated frequency bands by filtering and then to encode each of these subbands using a bit allocation rationale matched to the signal energy in that subband. The actual coding of the subband signal can be done using waveform encoding techniques such as PCM, DPCM and vector quantizer(VQ) in order to obtain higher data compression. Most researchers have focused on the error in the quantizer, but not on the overall reconstruction error and its dependence on the filter bank. This paper provides a thorough analysis of subband codecs and further development of optimum filter bank design using vector quantizer. We compute the mean squared reconstruction error(MSE) which depends on N the number of entries in each code book, k the length of each code word, and on the filter bank coefficients. We form this MSE measure in terms of the equivalent quantization model and find the optimum FIR filter coefficients for each channel in the M-band structure for a given bit rate, given filter length, and given input signal correlation model. Specific design examples are worked out for 4-tap filter in 2-band paraunitary filter bank structure. These optimum paraunitary filter coefficients are obtained by using Monte Carlo simulation. We expect that the results of this work could be contributed to study on the optimum design of subband codecs using vector quantizer.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.23 no.7
• /
• pp.1797-1806
• /
• 1998

Future satellite communication systems will be developed at Ka-band (20/30 GHz) owing to the relatively wide frequency allocation and current freedom from terrestrial interference for multimedia services. A serious disadvantage of the Ka-band, however, is the very high atmospheric attenuation in rainy weather. Synchronous CDMA drastically redces the effect of self-noise with several interesting features of CDMA for mobile communications such as fixible freuqncy rese, the capability of performin soft-handover and a lower sensitivity to interference. This paper evaluates the performance of a synchronous CDMA reture link for a Ka-band geostationary satellite communication system. For a fixed satellite channel whose characteristics depend on weather conditions, the signal envelope and phase for this channel is modelled as Gaussian. The bit error and outage probability, and the detection loss due to imperfect chip timing synchronization is analytically evaluated and the system capacity degaradation due to the weather condition is estimated. The two cases consist of the general case in which all users are affected by rain condition, and the worst case in which the reference user is only affected by rain attenuation. the results for two cases of rain condition clearly show that synchronous CDMA eases the power control requirements and has less sensitivity to imperfect power control.

• The Journal of the Acoustical Society of Korea
• /
• v.32 no.2
• /
• pp.95-103
• /
• 2013

An underwater acoustic (UWA) communication in shallow water is strongly affected by the water surface and the seabed acoustical properties. Every reflected signal to receiver experiences a time-variant scattering in sea surface roughness and a grazing-angle-dependent reflection loss in bottom. Consequently, the performance of UWA communication systems is degraded, and high-speed digital communication is disrupted. If there is a dominant signal path such as a direct path, the received signal is modeled statistically as Rice fading but if not, it is modeled as Rayleigh fading. However, it has been known to be very difficult to reproduce the statistical estimation by real experimental evaluation in the sea. To give an insight for this scattering and grazing-angle-dependent bottom reflection loss effect in UWA communication, authors conduct experiments to quantify these effects. The image is transmitted using binary frequency shift keying (BFSK) modulation. The quality of the received image is shown to be affected by water surface scattering and grazing-angle-dependent bottom reflection loss. The analysis is based on the transmitter to receiver range and the receiver depth dependent image quality and bit error rate (BER). The results show that the received image quality is highly dependent on the transmitter-receiver range and receiver depth which characterizes the channel coherence bandwidth.