• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1357-1370
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• 2000

In this paper, we investigate the performance of asynchronous multiple-chip-rate (MCR)-DS/CDMA systems, where singles are transmitted at different chip rates, processing gains, and transmitted powers according to the required services and their own bit rates. A simplified expression for the improved Gaussian approximation (SEIGA), which is hewn for as a very accurate and simple tool for the performance evaluation, is applied to MCR systems, The correlations between chip waveforms and integrations are utilized instead of correlations between chip sequences which are used in conventional method [6] [7][8], and since this approach makes use of the system model parameter directly, we obtain more direct relationship among system parameters. Simulation results show that the performance of MCR-DS/CDMA systems can be evaluated more accurately by using the proposed procedure than by using the GA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.10
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• pp.824-831
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• 2013

The delta driven GMSK is a modulation scheme to generate the gaussian pulse by the bipolar delta signal and to modulate the phase function with the differential gaussian pulse between $+T_b/2$ and $-T_b/2$. The demodulation of delta driven GMSK differs from conventional GMSK schemes. This paper proposed a demodulation with the differential phase detector at the end of each bit interval. A designed detector then finds the one of the possible region by hard decision, in which the phase difference lies. Finally the binary data can be recovered by state transition process. Through the BER simulation for AWGN channel, it was found that the proposed demodulation effected by the run length of binary data. The simulated BER degradation of about 2[dB] was analyzed, as compared to the theoretical coherent demodulation with $BT_b$=0.3.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.51-57
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• 2014

In this paper, we introduce the adaptive threshold detection scheme based on an evolutionary arithmetic algorithm for the M-ary holographic data storage(HDS) system. The genetic algorithm is a particular class of evolutionary arithmetic based on the process of biological evolution, which is a very promising technique for optimization problem and estimation applications. In this study, to improve the detection performance that is degraded by the HDS channel environment and the pixel misalignment, the threshold value was assumed to be a population set of the evolutionary algorithm. The proposed method can find an appropriate population set of bit threshold, which minimizes bit error rate(BER) as increased generation. For performance evaluation, we consider severe misalignment effect in the 4-ary holographic data storage system. Furthermore, we measure the BER performance and compare the proposed methods with the conventional threshold detection scheme, which verifies the superiority of the proposed scheme.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.722-725
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• 2010

In this paper, BER performance and error convergence speed of layered LDPC(Low Density Parity Check) decoder which supports IEEE 802.16e WiMAX standard is analyzed, and optimal design conditions for hardware implementation are derived. A LDPC decoder is modeled and simulated at AWGN channel with QPSK modulation by Matlab. The parity check matrix(PCM) for IEEE 802.16e standard which has block lengths of 576, 1440, 2304 and code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 are used. Fixed-point simulation results show that fixed-point bit-width should be more than 8 bits for acceptable decoding performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4A
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• pp.414-422
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• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5C
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• pp.498-504
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• 2009

A high-performance low-complexity decoding algorithm for LDPC codes is proposed in this paper, which has the advantages of both bit-flipping (BF) algorithm and sum-product algorithm (SPA). The proposed soft bit-flipping algorithm requires only simple comparison and addition operations for computing the messages between bit and check nodes, and the amount of those operations is also small. By increasing the utilization ratio of the computed messages and by adopting nonuniform quantization, the signal-to-noise ratio (SNR) gap to the SPA is reduced to 0.4dB at the frame error rate of 10-4 with only 5-bit assignment for quantization. LDPC codes with high column or row weights, which are not suitable for the SPA decoding due to the complexity, can be practically implemented without much worsening the error performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11B
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• pp.1522-1533
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• 2001

In this paper, we handle the estimation method of the received $E_{b}l1_{o}$ for forward closed-loop power control in cdma2000 systems. The estimation of MS-received $E_{b}l1_{o}$ utilizes the symbols related to the forward power control subchannel transmission. The estimation of the received bit energy and noise variance is analyzed for the frequency-selective Rayleigh fading channel. In order to improve SIR (signal-to-interference), the estimation of the received bit energy is made by the coherent combining of the rake-fingers and received I/Q symbols. And, in this paper, we evaluate the performance of forward closed-loop power control according to the mobile speed and the power adjustment step size in terms of the bit error rate (BER) and power control error. Simulation results present the optimal power adjustment step sizes according to the mobile speeds.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.7B
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• pp.1021-1033
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• 2001

본 논문에서는 초광대역 시간 도약 임펄스 무선 전송 (ultra wideband time hopping impulse radio) 다원 접속 시스템을 위한 잡음 부호 기반의 새로운 시간 도약 시퀀스를 제안한다. 임펄스 무선 전송 시스템에 대한 지금까지의 연구에서는 대부분 이상적인 랜덤 시간 도약 시퀀스를 사용하여 여러 사용자가 다원 접속한다고 가정하였다. 본 논문에서는 동일 차수의 다수 m-시퀀스와 십진화기를 이용하여 구현 가능한 시간 도약 시퀀스를 제안하고, 여러 사용자의 동기식 및 비동기식 접속 상황에 대한 모의 실험을 통해 이상적인 랜덤 시퀀스와 유사한 우수한 비트오율 성능을 얻을 수 있음을 확인하였다. 또한 제안된 시간 도약 시퀀스를 사용하는 경우 좀 더 일반적인 상황인 비동기식 다원 접속이 동기식 다원 접속에 비해 우수한 성능을 얻을 수 있음을 분석한다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.173-175
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• 2014

In this paper, we compare a bit error rate performance with channel estimation for terrestrial cloud transmission systems in order to provide an advanced research. Since terrestrial cloud transmission systems experience co-channel interference from one or more transmitters, they have to operate under negative signal-to-noise ratio.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.278-280
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• 2010

본 논문에서는 채널의 전송대역폭이 제한되는 환경에서 성형 펄스로 RTPZD(root trapezoidal), RBTRC(root better than raised-cosine), 그리고 RRC(root raised-cosine)를 적용한 시스템의 BER(bit error rate) 성능을 컴퓨터 모의실험을 통하여 비교 분석하였다. 실험 결과 RBTRC는 RTPZD를 적용한 시스템보다 채널의 대역폭 제한에 더욱 민감하여, 채널의 전송대역 폭이 협소하여짐에 따라 RBTRC를 적용한 시스템의 BER 성능이 RTPZD의 성능보다 더 큰 폭으로 저하됨을 관찰할 수 있었 다. RBTRC 펄스는 심볼 타이밍 오차에 다른 성형 펄스보다 덜 민감한 장점이 있지만, 대역제한된 채널에서는 성능 저하가 크므로 성형 펄스로 RTPZD 또는 RRC 펄스를 적용하는 것이 더 유리하다고 판단된다.