• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.3
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• pp.69-75
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• 2011

In this paper, we propose an anycast event driven synchronization mechanism to reduce power overheads. Our proposed mechanism can reduce unnecessary polling operations on SHI(Snoop Hit Invalidate) or SHR(Snoop Hit Read) states. It prevents waisting bandwidth and reduces power overheads on polling operation. Also it decreases transition power of state change compared to broadcast model. Simulation results indicated that the proposed architecture had about 15.3% of power decrease compared to spin-lock model and about 4.7% of power decrease compared to broadcast model. Overall results indicated that proposed synchronization mechanism could increase power efficiency of multi-core system by reducing power overheads.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.1010-1011
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• 2015

최근 고효율 전력변환을 위해 LLC 공진형 하프브릿지 컨버터의 동기정류기에 대한 연구가 활발히 진행되고 있다. 기존 일반적인 다이오드 정류기를 사용하는 경우 출력전류에 비례하는 전력손실이 커서 대전력용으로 사용하기에는 적합하지 않다. 따라서 스위치를 이용한 동기정류기가 검토되고 있는데 동기정류기의 스위치를 구동시키기 위해서는 스위치를 구동시킬 수 있는 구동용 IC가 이용되고 있다. 동기정류기 구동 IC의 단점으로는 약 50%의 중부하 이하에서는 동작되지 않는 단점이 있어 이를 보완하기 위하여 변압기 1차측 전류를 검출하여 게이트 전압을 만들어 스위치를 구동시키는 회로를 제안하였다. 본 논문의 실험 결과 저전력 지점에서 동기정류기가 구동되었고 따라서 전력변환 효율은 기존의 다이오드 정류기에 비해 우수하며 효율개선효과가 있다는 것을 실험으로 보였다.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.7
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• pp.9-15
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• 1999

In this paper, we propose a bit synchronizer which is suitable for frequency hopping systems. The proposed bit synchronizer is an ADPLL in which the digital loop filter is combined with an error symbol detecting circuit. Suppressing the tracking process, when hop mute and impulse noises are detected, improves the performance of the digital loop filter and enhances the probability of the frequency hopping system. Simulation results demonstrate an improved performance of the proposed bit synchronizer compared with existing ones.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.33-42
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• 2003

This paper describes an efficient design of an asynchronous 16-bit divider using the NST (new Svoboda-Tung) algorithm. The divider is designed to reduce power consumption by using the asynchronous design scheme in which the division operation is performed only when it is requested. The divider consists of three blocks, i.e. pre-scale block, iteration step block, and on-the-fly converter block using asynchronous pipeline structure. The pre-scale block is designed using a new subtracter to have small area and high performance. The iteration step block consists of an asynchronous ring structure with 4 division steps for area reduction. In other to reduce hardware overhead, the part related to critical path is designed by a dual-rail circuit, and the other part is done by a single-rail circuit in the ring structure. The on-the-fly converter block is designed for high performance using the on-the-fly algorithm that enables parallel operation with iteration step block. The design results with 0.6${\mu}{\textrm}{m}$ CMOS process show that the divider consists of 12,956 transistors with 1,480 $\times$1,200${\mu}{\textrm}{m}$$^2$area and average-case delay is 41.7㎱.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.1
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• pp.70-77
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• 2008

On the wireless sensor network MAC protocols, one of main issues is energy enciency. Since several asynchronous wireless sensor network MAC protocols with short preamble sampling scheme can be operated without setting the timing synchronization among neighbor nodes, it consumes a little energy for maintaining protocols. However, each node encounters either preamble or data overhearing problem, because each node wakes up in a different time and must check whether the frame is being sent to itself or not. To solve this overhearing problem, we newly propose B-MAC++ that can reduce the overhearing energy consumption by using short preambles with destination address and payload length. from simulation results, we show that the proposed B-MAC++ has advantageous in terms of power consumption efficiency over other asynchronous wireless sensor network MAC protocols.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.883-890
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• 2015

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.253-261
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• 2013

In this paper, we study the problem of controlling composite asynchronous sequential machines. The considered asynchronous machine consists of two input/state machines in cascade connection, where the output of the front machine is delivered to the input channel of the rear machine. The objective is to design a corrective controller realizing model matching such that the stable state behavior of the closed-loop system matches that of a reference model. Since the controller receives the state feedback of the rear machine only, there exists uncertainty about the present state of the front machine. We specify the existence condition for a corrective controller given the uncertainty. The design procedure for the proposed controller is described in a case study.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.195-204
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• 1996

We suggest a transform method form asynchronous finite state machines (AFSMs) into signal transition graphs (STGs) for speed-independent circuit synthesis. Existing works synthesize nodes in the state graph increases exponentially as the number of input and output signals increases. To overcome the problem of the exponential data complexity, we transform AFSMs into STGs so that the previous synthesis algorihtm form STGs can be applied.Accoridng to the experimental results, it turns out that our synthesis method produces more efficient circuit than the previous synthesis methods.

• Korean Journal of Optics and Photonics
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• v.20 no.3
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• pp.143-147
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• 2009

We propose an asymmetrical 2.5 Gbps / 622 Mbps bidirectional optical subscriber network with Manchester coded downstream and NRZ (Non-Return-to-Zero) upstream remodulation. The proposed system has important characteristics in the optical network unit (ONU): it does not require a light source or the usual control circuits such as wavelength control and output power control, and it is possible to use a synchronization scheme between upstream and downstream data. We theoretically analyze BER(Bit Error Rate) performance of upstream data remodulated with Manchester coded downstream according to the types of NRZ downstream data and perform simulations with MATLAB. The BER performance and the receiver sensitivity have been improved by 3 dB by adjusting threshold levels compared to the conventional receiver. The results have shown the remodulation scheme with Manchester coded downstream could be a useful technology for asynchronous and asymmetric optical subscriber networks with low cost and simple structures.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.335-343
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• 2012

This paper presents an target tracking algorithm for fusion of radar and infrared(IR) sensor measurement data. Generally, fusion methods with Kalman filter assume that processing data obtained by radar and IR sensor are synchronized. It has much limitation to apply the fusion methods to real systems. A key point which is taken into account in the proposed algorithm is the fact that two asynchronous dissimilar data are fused by compensating the time difference of the measurements using radar's ranges and track state vectors. The proposed fusion algorithm in the paper is evaluated via a computer simulation with the existing track fusion and measurement fusion methods.