• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1735-1740
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• 2005

SoC design integrates many IPs that operate at different frequencies and the use of the different clock for each IP makes the design the most effective one. An asynchronous FIFO is required as a kind of a buffer to connect IPs that are asynchronous. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, an asynchronous FIFO is designed to transfer data across asynchronous clock domains by using a valid bit scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the Bate level to compare with other FIFO scheme. The subject mater of this paper is under patent pending.

• The Transactions of the Korea Information Processing Society
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• v.5 no.11
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• pp.2980-2988
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• 1998

This paper describes the design of asynchronous adders based on carry selection and carry bypass techniques. The designs are faster than existing asynchronous adders which are based on ripple carry technique. It is caused by reducing the carry transfer time by using carry selection and carry bypass techniques. Also, the design uses tree structure to reduce the completion sensing time. The proposed adders are designed with CMOS domino logic and experimented with HSPICE simulator. Experimental results show that the proposed adders can be faster about 50% in average cases than previous ripple carry adders.

• Journal of Advanced Navigation Technology
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• v.7 no.1
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• pp.6-13
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• 2003

In this paper, a non-coherent code tracking loop is designed for 3GPP HSDPA MODEM and its performance is analyzed in terms of steady-state jitter variance and transient response characteristics. Analytical closed-form formula for steady-state jitter variance is first derived for AWGN environments as a function of pulse-shaping filter, timing offset, signal-to-interference ratio, and loop bandwidth. Also obtained is the transient response characteristic of a tracking loop. Finally, the performance of the designed tracking loop is confirmed by computer simulations.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.4
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• pp.1-10
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• 2008

The problem of controlling asynchronous sequential machines is addressed in this paper. Corrective control means to make behavior of an asynchronous sequential machine equal to that of a given model. The main objective is to develope a corrective controller, especially when a model is given as nondeterministic, or a set of reference models. The structure of corrective control system for asynchronous sequential machines is addressed first, followed by description of nondeterministic models. Then, we propose a method for analyzing reachability of asynchronous machines and nondeterministic models. Proposed methods are demonstrated in an example.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.61-74
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• 2002

This paper presents a method which synthesizes asynchronous circuits from free-choice Signal Transition Graphs (STGs) with timing constraints. The proposed method synthesizes asynchronous circuits by analyzing: the relations between signal transitions directly from the STGs without generating state graphs. The synthesis procedure decomposes a free-choice STG into deterministic STGs which do not have choice behavior. Then, a timing analysis extracts the timed concurrency and tamed causality relations between any two signal transitions for each deterministic STG. The synthesis procedure synthesizes circuits for each deterministic STG and synthesizes the final circuit by merging the circuits for each deterministic STG. The experimental results show that our method achieves significant reductions in synthesis time for the circuits which have a large state space, and generates circuits that have nearly the same area as compared to previous methods.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.4
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• pp.39-48
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• 2009

Asynchronous sequential machines, or clockless logic circuits, have several advantages over synchronous machines such as fast operation speed, low power consumption, etc. In this paper, we propose a novel robust controller for input/output asynchronous sequential machines with uncertain state transitions. Due to model uncertainties or inner failures, the state transition function of the considered asynchronous machine is not completely known. In this study, we present a formulation to model this kind of asynchronous machines ana using generalized reachability matrices, we address the condition for the existence of an appropriate controller such that the closed-loop behavior matches that of a prescribed model. Based on the previous research results, we sketch design procedure of the proposed controller and analyze the stable-state operation of the closed-loop system.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.3
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• pp.399-408
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• 2022

This paper proposes a corrective control system to achieve fault-tolerant control for input/output asynchronous sequential circuits vulnerable to transient faults violating fundamental mode operations. To overcome non-fundamental mode faults occurring in transient transitions of asynchronous sequential circuits, it is necessary to determine the end of unauthorized state transitions caused by the faults and to stably take the circuit from the faulty state to a desired state that is output equivalent with the normal next stable state. We address the existence condition for a proper output-feedback corrective controller that achieves fault diagnosis and fault-tolerant control for these non-fundamental mode faults. The corrective controller and asynchronous sequential circuit are implemented on field-programming gate array to demonstrate the synthesis procedure and applicability of the proposed control scheme.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.1
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• pp.241-250
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• 2000

Chua's circuit is a simple electronic network which exhibits a variety of bifurcation and attractors. The circuit consists of two capacitors, an inductor, a linear resistor, and a nonlinear resistor. In this paper, a transmitter and a receiver using two identical Chua's circuits are proposed and synchronizations and secure communication of a lossy equivalent transmission are investigated. Since the synchronization of the lossy equivalent transmission system is impossible by coupled synchronization, theory having both the drive-response and the coupled synchronization is proposed. The proposed method is synthesizing the desired information with the chaos circuit by adding the information signal to the chaos signal in the lossy equivalent transmission system.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.7-9
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• 2001

ASIC 설계에서 gated clock으로 동작하는 clock을 입력으로 받는 회로들은 스캔 테스트를 수행하기에 용이하지 않다. 이러한 회로들에 대하여 스캔 테스트기법을 적용하기 위한 설계변경기술을 제안한다. 제안하는 설계변경기술은 비동기 회로를 동기 회로로 변환함으로써 스캔 기법을 적용할 수 있는 회로로 변환하게 된다. 이로써 테스트를 좀 더 용이하게 수행할 수 있을 뿐 아니라 결함 시험도를 높이게 되는 효과를 가져올 수 있다.

• Journal of Advanced Navigation Technology
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• v.1 no.1
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• pp.70-80
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• 1997

In this paper, the performances of two noncoherent code tracking loops, i. e., traditional code tracking loop(TCTL) and modified code tracking loop(MCTL) are analyzed and compared in a CDMA mobile environment. Closed-form formulas for steady-state jitter variance are derived analytically for the two schemes as a function of the pulse shaping filter, timing offset, signal-to-interference ratio, and loop bandwidth. The design issues of the loop filter are also addressed with emphasis on the second-order tracking loop. Finally, the degradation of BER performance due to timing errors is examined in a CDMA reverse link for IMT-2000 designed by ETRI.