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A Design of Pipelined Adaptive Decision-Feedback Equalized using Delayed LMS and Redundant Binary Complex Filter Structure (Delayed LMS와 Redundant Binary 복소수 필터구조를 이용한 파이프라인 적응 결정귀환 등화기 설계)

  • An, Byung-Gyu;Lee, Jong-Nam;Shin, Kyung-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.12
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    • pp.60-69
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    • 2000
  • This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

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Disturbance Rejection and Attitude Control of the Unmanned Firing System of the Mobile Vehicle (이동형 차량용 무인사격시스템의 외란 제거 및 자세 제어)

  • Chang, Yu-Shin;Keh, Joong-Eup
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.44 no.3
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    • pp.64-69
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    • 2007
  • Motion control of the system is a position control of motor. Motion control of an uncertain robot system is considered as one of the most important and fundamental research directions in the robotics. Some distinguished works using linear control, adaptive control, robust control strategies based on computed torque methodology have been reported. However, it is generally recognized within the control community that these strategies suffer from the following problems : the exact robot dynamics are needed and hard to implement, the adaptive control cannot guarantee the performance during the transient period for adaptation under the variation, the robust control algorithms such as the sliding mode control need information on the bounds of the possible uncertainty and disturbance. And it produces a large control input as well. In this dissertation, a motion control for the unmanned intelligent robot system using disturbance observer is studied. This system is affected with an impact vibration disturbance. This paper describes a stable motion control of the system with the consideration of external disturbance. To obtain the stable motion independently against the external disturbance, the disturbance rejection is strongly required. To address the above issue, this paper presents a Disturbance OBserver(DOB) control algorithm. The validity of the suggested DOB robust control scheme is confirmed by several computer simulation results. And the experiments with a motor system is performed to give the validity of applicability in the industrial field. This results make the easier implementation of the controller possible in the field.

Joint Optimization of the Motion Estimation Module and the Up/Down Scaler in Transcoders television (트랜스코더의 해상도 변환 모듈과 움직임 추정 모듈의 공동 최적화)

  • Han, Jong-Ki;Kwak, Sang-Min;Jun, Dong-San;Kim, Jae-Gon
    • Journal of Broadcast Engineering
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    • v.10 no.3
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    • pp.270-285
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    • 2005
  • A joint design scheme is proposed to optimize the up/down scaler and the motion vector estimation module in the transcoder system. The proposed scheme first optimizes the resolution scaler for a fixed motion vector, and then a new motion vector is estimated for the fixed scaler. These two steps are iteratively repeated until they reach a local optimum solution. In the optimization of the scaler, we derive an adaptive version of a cubic convolution interpolator to enlarge or reduce digital images by arbitrary scaling factors. The adaptation is performed at each macroblock of an image. In order to estimate the optimal motion vector, a temporary motion vector is composed from the given motion vectors. Then the motion vector is refined over a narrow search range. It is well-known that this refinement scheme provides the comparable performance compared to the full search method. Simulation results show that a jointly optimized system based on the proposed algorithms outperforms the conventional systems. We can also see that the algorithms exhibit significant improvement in the minimization of information loss compared with other techniques.

DFT를 사용한 고속 constant modulus algorithm 의 성능분석

  • Yang, Yoon-Gi;Lee, Chang-Su;Yang, Soo-Mi
    • Journal of IKEEE
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    • v.13 no.1
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    • pp.1-10
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    • 2009
  • Recently, some frequency domain CMA (Constant Modulus Algorithm) have been introduced in an effort to reduce computational complexities [1,2]. In [1], a fast algorithm that minimizing cost function designed for block input signal is employed, while in [2], a novel cost function that minimizing sample by sample input is used. Although, the two fast algorithm save computational complexities as compared to CMA, the convergence behaviors of the two fast algorithm show different results with repsect to CMA. Thus, in this paper, some analytical results on the error surface of the fast frequency domain CMA are introduced. From the analytical results, we show that the more recent algorithm [2] outperforms the previous algorithm [1]. Simulation results reveals that the recent algorithm [2] shows 50% enhanced convergence with respect to the old fast algorithm [1]. Also, we show that the recent fast algorithm [2] has comparable convergence performance with respect to conventional CMA algorithm.

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Digital Predistortion for Multi-band/Multi-mode Transmission Systems (다중 대역 전송 시스템을 위한 전치왜곡 알고리즘)

  • Choi, Sung-Ho;Lee, Byung-Hwan;Lee, Chul-Soo;Jeong, Eui-Rim
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.1
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    • pp.48-58
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    • 2012
  • New digital predistortion technique is proposed for power amplifier linearization in multi-band transmission systems. We consider a system where muli-band signals are combined and amplified by a single power amplifier (PA). In this system, the PA output is distorted by the nonlinear cross-products between different band signals as well as their own nonlinear self-products. To compensate these nonlinear effects, we propose a multiple PD structure. Each PD removes the nonlinear cross-products and self-products to mitigate the spectral regrowth for the corresponding band. Since the PD parameters for different bands are linked together, it is difficult to find the PD parameters separately. Thus, we propose an iterative method for finding the PD parameters jointly. For demonstration of the proposed method, multi-band characteristics of PA are extracted from a commercial power amplifier. Computer simulation was executed based on the PA parameters. The simulation results show that the proposed method can effectively linearize the PA and remove spectral regrowth at each signal band.

A SOC Design Methodology using SystemC (SystemC를 이용한 SOC 설계 방법)

  • 홍진석;김주선;배점한
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.153-156
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    • 2000
  • This paper presents a SOC design methodology using the newly-emerging SystemC. The suggested methodology firstly uses SystemC to define blocks from the previously-developed system level algorithm with internal behavior and interface being separated and validate such a described blocks' functionality when integrated. Next, the partitioning between software and hardware is considered. With software, the interface to hardware is described cycle-accurate and the other internal behavior in conventional ways. With hardware, I/O transactions are refined gradually in several abstraction levels and internal behavior described on a function basis. Once hardware and software have been completed functionally, system performance analysis is performed on the built model with assumed performance factors and influences such decisions regressively as on optimum algorithm selection, partitioning and etc. The analysis then gives constraint information when hardware description undergoes scheduling and fixed-point trans- formation with the help of automatic translation tools or manually. The methodology enables C/C++ program developers and VHDL/Verilog users to migrate quickly to a co-design & co-verification environment and is suitable for SoC development at a low cost.

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Study on the Effective Compensation of Quantization Error for Machine Learning in an Embedded System (임베디드 시스템에서의 양자화 기계학습을 위한 효율적인 양자화 오차보상에 관한 연구)

  • Seok, Jinwuk
    • Journal of Broadcast Engineering
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    • v.25 no.2
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    • pp.157-165
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    • 2020
  • In this paper. we propose an effective compensation scheme to the quantization error arisen from quantized learning in a machine learning on an embedded system. In the machine learning based on a gradient descent or nonlinear signal processing, the quantization error generates early vanishing of a gradient and occurs the degradation of learning performance. To compensate such quantization error, we derive an orthogonal compensation vector with respect to a maximum component of the gradient vector. Moreover, instead of the conventional constant learning rate, we propose the adaptive learning rate algorithm without any inner loop to select the step size, based on a nonlinear optimization technique. The simulation results show that the optimization solver based on the proposed quantized method represents sufficient learning performance.

Low-Power Implementation of A Multichannel Hearing Aid Using A General-purpose DSP Chip (범용 DSP 칩을 이용한 다중 채널 보청기의 저전력 구현)

  • Kim, Bum-Jun;Byun, Joon;Park, Young-Cheol
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.11 no.1
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    • pp.18-25
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    • 2018
  • In this paper, we present a low-power implementation of the multi-channel hearing aid system using a general-purpose DSP chip. The system includes an acoustic amplification algorithm based on Wide Dynamic Range Compression (WDRC), an adaptive howling canceller, and a single-channel noise reduction algorithm. To achieve a low-power implementation, each algorithm is re-constructed in forms of integer program, and the integer program is converted to the assembly program using BelaSigna(R) 250 instructions. Through experiments using the implementation system, the performance of each processing algorithm was confirmed in real-time. Also, the clock of the implementation system was measured, and it was confirmed that the entire signal processing blocks can be performed in real time at about 7.02MHz system clock.

A Temporal Error Concealment Method Based on Edge Adaptive Masking (에지정보에 적응적인 마스크를 이용한 시간방향 오류 은닉 방법)

  • Kim Yong-Woo;Lim Chan;Kang Hyun-Soo
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.42 no.3 s.303
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    • pp.91-98
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    • 2005
  • In this paper, we propose a temporal error concealment method based on the edge adaptive masking. In the method, four regions around the corrupted block - top, bottom, left, and right - are defined and the edge features of the regions are extracted by applying an edge operator for each direction. The size of a mask for the boundary matching is determined by the edge information, which can be considered as a criterion to measure the activity of the boundary region. In other words, it is determined such that the size of the mask is proportional to the amount of edge-component extracted from each region in order to yield the higher reliability on boundary matching. This process is equivalent to applying weights depending on the edge features, which leads the improved motion vector. In experiments, it is verified that the proposed method outperforms the conventional methods in terms of image quality, and then its merits and demerits are discussed.

Adaptive Intra Frame Encoding for H.264/AVC (H.264/AVC를 위한 적응적 인트라 프레임 압축)

  • Park, Sang-Hyun
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.12
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    • pp.1447-1454
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    • 2014
  • In H.264 standard, an intra frame is the first frame of a GOP (Group of Pictures) and all macroblocks of an intra frame are encoded using the same quantization parameter. In addition, an intra frame is used for encoding the following frames of the same GOP so the encoding results of an intra frame affect the encoding results of the entire GOP. Thus, it is important to find the optimal quantization parameter of an intra frame for improving the quality of a GOP. In this paper, we propose an searching method for an optimal quantization parameter of an intra frame in real time. The proposed method uses a gradient descent method to find the optimal value based on characteristics of the optimal quantization parameters. Experimental results show that the proposed method captures the characteristics of the optimal quantization parameter and accurately estimates the optimal value.