• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.44 no.1
• /
• pp.102-112
• /
• 2007

This paper includes an analysis of face recognition algorithm to design hardware and presents fixed point model in accordance with it. Face recognition algorithm detects the positions of face and eyes to make use of their feature data to detect and verify human faces. It distinguishes a particular user by means of comparing them with registered face features. To implement the face recognition algorithm into hardware, we developed its fixed point model by analyzing face feature parameters, face acquisition data, and feature detection parameters and operation structure.

• The KIPS Transactions:PartB
• /
• v.13B no.4 s.107
• /
• pp.429-438
• /
• 2006

Neural Networks(NNs) are applied for solving a wide variety of nonlinear problems in several areas, such as image processing, pattern recognition etc. Although NN can be simulated by using software, many potential NN applications required real-time processing. Thus they need to be implemented as hardware. The hardware implementation of multi-layer perceptrons(MLPs) in several kind of NNs usually uses a fixed-point arithmetic due to a simple logic operation and a shorter processing time compared to the floating-point arithmetic. However, the fixed-point arithmetic-based MLP has a drawback which is not able to apply the MLP software that use floating-point arithmetic. We propose a design method for MLPs which has the floating-point arithmetic-based fully-pipelining architecture. It has a processing speed that is proportional to the number of the hidden nodes. The number of input and output nodes of MLPs are generally constrained by given problems, but the number of hidden nodes can be optimized by user experiences. Thus our design method is using optimized number of hidden nodes in order to improve the processing speed, especially in field of a repeated processing such as image processing, pattern recognition, etc.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.46 no.1
• /
• pp.95-103
• /
• 2009

We improve the performance of WCDMA repeater by cancelling the feedback interference radio signal under the fixed point implementation. Floating-point DSP or FPGA to implement the ICS algorithm may have an disadvantage of high cost, To solve this problem, we suggest the ICS algorithm based on LMS under fixed point operation, and show the validity of our results by comparing with the floating-point results through numerical simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.6
• /
• pp.49-59
• /
• 2008

SIFT(Scale Invariant Feature Transform) is an algorithm to extract vectors at pixels around keypoints, in which the pixel colors are very different from neighbors, such as vortices and edges of an object. The SIFT algorithm is being actively researched for various image processing applications including 3-D image constructions, and its most computation-intensive stage is a keypoint localization. In this paper, we develope a fixed-point model of the keypoint localization and propose its efficient hardware architecture for embedded applications. The bit-length of key variables are determined based on two performance measures: localization accuracy and error rate. Comparing with the original algorithm (implemented in Matlab), the accuracy and error rate of the proposed fixed point model are 93.57% and 2.72% respectively. In addition, we found that most of missing keypoints appeared at the edges of an object which are not very important in the case of keypoints matching. We estimate that the hardware implementation will give processing speed of $10{\sim}15\;frame/sec$, while its fixed point implementation on Pentium Core2Duo (2.13 GHz) and ARM9 (400 MHz) takes 10 seconds and one hour each to process a frame.

• (The)Study of the Eastern Classic
• /
• no.41
• /
• pp.275-301
• /
• 2010

Confucius made endless thoughts on such themes as enlightening for the internal value of human, how to draw out such value and how to make personal relationship in order to overcome the chaotic Chun-qiu age. The spirit of 'Harmony but not Sameness' stated by Confucius passes us the theoretical meaning for making a good relationship with the others, which is realization of Benevolence. The spirit of 'Harmony but not Sameness' pursues moral, public and golden-mean value. This pursuit is made to look for harmonization and coexistence in personal relation, community based relation and, furthermore, relation with the nature, so that a great man is an entirely-good person who has realized the spirit of 'Harmony but not Sameness'. The spirit of 'Harmony but not Sameness' throws to us many issues to think of for the social unity, 'living together', which is the central theme of today. The objects for which the 'living together' shall be embodied are the minor groups of our society and those who are relatively expelled from the power and benefit including multi-culture based families, north Korean refugees and etc. Such open mind for harmonization and coexistence gives us, furthermore, another important issue to think of also in the matter of environment that includes the ecosystem and the entire nature.

• The KIPS Transactions:PartA
• /
• v.12A no.2 s.92
• /
• pp.95-102
• /
• 2005

The Newton-Raphson iterative algorithm for finding a floating point reciprocal which is widely used for a floating point division, calculates the reciprocal by performing a fixed number of multiplications. In this paper, a variable latency Newton-Raphson's reciprocal algorithm is proposed that performs multiplications a variable number of times until the error becomes smaller than a given value. To find the reciprocal of a floating point number F, the algorithm repeats the following operations: '$'X_{i+1}=X=X_i*(2-e_r-F*X_i),\;i\in\{0,\;1,\;2,...n-1\}'$ with the initial value $'X_0=\frac{1}{F}{\pm}e_0'$. The bits to the right of p fractional bits in intermediate multiplication results are truncated, and this truncation error is less than $'e_r=2^{-p}'$. The value of p is 27 for the single precision floating point, and 57 for the double precision floating point. Let $'X_i=\frac{1}{F}+e_i{'}$, these is $'X_{i+1}=\frac{1}{F}-e_{i+1},\;where\;{'}e_{i+1}, is less than the smallest number which is representable by floating point number. So, $X_{i+1}$ is approximate to $'\frac{1}{F}{'}$. Since the number of multiplications performed by the proposed algorithm is dependent on the input values, the average number of multiplications per an operation is derived from many reciprocal tables $(X_0=\frac{1}{F}{\pm}e_0)$ with varying sizes. The superiority of this algorithm is proved by comparing this average number with the fixed number of multiplications of the conventional algorithm. Since the proposed algorithm only performs the multiplications until the error gets smaller than a given value, it can be used to improve the performance of a reciprocal unit. Also, it can be used to construct optimized approximate reciprocal tables. The results of this paper can be applied to many areas that utilize floating point numbers, such as digital signal processing, computer graphics, multimedia scientific computing, etc.

• Proceedings of the Korean Nuclear Society Conference
• /
• 1998.05b
• /
• pp.78-83
• /
• 1998

Alloy 600과 Alloy 690의 응력부식파괴(Stress corrosion cracking, SCC)에 미치는 TiO$_2$의 영향을 315$^{\circ}C$의 10%NaOH 수용액에서 RUB(reverse U-bend) 시편, C-Ring 시편과 CT(compact tension)시편을 사용하여 평가하였다. 시편은 alloy 600 MA(mill anneal), alloy 600 TT(thermal treatment) 그리고 alloy 690 TT로 제작하였다. SCC 시험은 탈산된 10%NaOH 수용액에 2 g/1 TiO$_2$를 첨가한 용액과 첨가하지 않은 용액에서 수행하였으며, 이 조건에서 분극곡선도 얻었다. SCC 시험시 시편을 부식전위로부터 +150 ㎷ 양극분극을 가하였다. 기준전극으로 external Ag/AgCl electrode를 사용하였다. Alloy 600 MA로 제작한 RUB 시편은 TiO$_2$가 없는 용액에서 5일 안에 벽 관통 균열을 보였으나 TiO$_2$가 첨가된 용액에서는 균열을 관찰할 수 없었다. TiO$_2$가 첨가됨에 따라 alloy 600과 alloy 690의 임계전류밀도는 크게 감소하였고 또한 부동태 전류밀도도 감소하였다. 부동테 영역에서 TiO$_2$가 있는 용액의 경우 여러 peak가 있는 반면에 TiO$_2$가 없는 용액은 peak가 뚜렷하지 않았다. 이런 결과는 TiO$_2$가 첨가점에 따라 active region에서도 안정한 부동태 피막이 존재한다는 것을 시사한다. 또한 TiO$_2$가 없는 경우 SCC가 잘 일어나는 영역에 존재하는 부동태 피막이 TiO$_2$ 첨가에 따라 repassivation kinetics 등의 성질이 변화한 것으로 판단된다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.12A
• /
• pp.1912-1923
• /
• 2000

본 논문에서는 내장된 자체 테스트(BIST: Built-In Self Test) 기법의 구현에 관해 기술한다. 내장된 자체 테스트 기법이 적용된 칩은 영상 처리 및 3차원 그래픽스용 부동 소수점 DSP 코어인 FLOVA이다. 내장된 로직 자체 테스트 기법은 FLOVA의 부동 소수점 연산 데이터 패스에 적용하였으며, 내장된 메모리 자체 테스트 기법은 FLOVA에 내장된 데이터 메모리와 프로그램 메모리에 적용하였다. 그리고, 기판 수준의 테스팅을 지원하기 위한 표준안인 경계 주사 기법(IEEE 1149.1)을 구현하였다. 특히, 내장된 자체 테스트 로직을 제어할 수 있도록 경계주사 기법을 확장하여 적용하였다.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.20 no.4
• /
• pp.24-29
• /
• 1983

In this paper, a floating-point processor which satisfied the subset of the proposed IEEE standard has been designed and realized by TTL chips. This processor consists of a floating-point arithmetic unit and a control sequencer. AHPL has been used in the design of sequencer. The execution times for the arithmetic operations were measured and compared with other microprocessor. The results had shown faster operations compared to the Z-80 processor. Though this processor was built by TTL chips, it could be fabricated as a one-chip processor.

• Proceedings of the Korean Information Science Society Conference
• /
• 2007.10b
• /
• pp.194-197
• /
• 2007

본 논문에서는 모바일용 3차원 그래픽 라이팅 엔진을 위한 부동소수점 멱승기클 제안한다. 3D 그래픽의 라이팅 과정은 연산량이 많고, 복잡하기 때문에 각 연산 유닛들이 저비용으로 빠르게 연산을 수행해야 한다. 본 논문에서 제안한 멱승기는 처리율을 높이기 위해 파이프라인 구조를 사용하였으며, $10^{-4}$의 정확도를 만족한다. 전체 구조는 5 stage로 구성되며, 크게 로그연산기와 지수연산기로 이루어져 있다. 일반적으로 로그연산기는 정확도를 높이기 위하여 큰 롬 테이블을 사용하는데, 이는 많은 면적을 차지하게 된다. 이러한 롬 테이블 면적 문제를 해결하기 위하여 Newton method을 사용하여 롬 테이블의 사이즈를 줄였다. 또한 오일러 상수를 밑으로 하는 지수연산기도 입력 비트의 크기를 줄이고, 테이블의 개수를 늘림으로써 롬 테이블의 크기를 줄였다. 지수연산의 밑은 부동소수점 포맷으로 [0, 1]의 범위를 가지며, 승은 정수 포맷으로 [0, 128]의 범위를 갖는다. Magnachip $0.18{\mu}m$ 공정에서 100Mhz의 동작주파수를 만족하였으며, 약 16k gates을 차지한다.