• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.74-76
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• 2007

This paper presents the hardware design of a 32bit floating point based processor. The processor can perform nonlinear functions such as sinusoidal functions, exponential functions, and other nonlinear functions. Using the Taylor series and the Newton - Raphson method, nonlinear functions are approximated. The processor is actually embedded on an FPGA chip and tested. The numerical accuracy of the functions is compared with those computed by the MATLAB.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2006.11a
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• pp.141-144
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• 2006

In this paper, using the notion of generalized metric (or D-metric) due to Dhage [3], we give new definition of M-fuzzy metric spaces and prove a common fixed point theorem for two mappings under the condition of weak compatible and R-weakly commuting mappings in complete M-fuzzy metric spaces.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• fall
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• pp.68-69
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• 2021

본 논문에서는 JPEG Pleno에서 제공하는 디지털 홀로그램 표준화 데이터를 압축하는 방법을 제시한다. 디지털 홀로그램의 수치 복원에서 시각화를 위한 랜덤 위상의 추가는 간섭현상으로 인한 스페클 노이즈와 더블어 홀로그램의 압축 효율을 떨어트린다. 홀로그램은 완전 복소의 부동소수점 형태의 데이터로 구성되며 초고해상도와 스페클 노이즈로 인해 홀로그램 특성에 맞춘 압축기술 개발이 필수적이다. 먼저, 다양한 웨이블릿 필터를 이용하여 홀로그램 데이터에 대한 주파수 특성 분석을 진행하여 필터 종류에 따른 에너지 집중도를 분석한다.

• Journal of Digital Convergence
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• v.10 no.6
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• pp.181-187
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• 2012

This study inquires into what effect the tax burden of investors, for typical taxes related to real estate investment; acquisition tax, comprehensive real estate holding tax, and transfer income tax, might have on the real estate investment behaviors; the purpose of long-term investment. These real estate investment behaviors have been analyzed to see how much they affect investment performance such as realized compound yield. This study model, which considers the fact that the choice of investment behavior for the degree of tax burden of investors may lead to different results in real estate investment, is expected to be an effective decision-making tool for investment.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.4
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• pp.457-463
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• 2010

In this study I hope to answer the questions, "In real estate marketing, what are the steps on Purchase and Postpurchase Behavior in Real Estate Marketing?" The findings of this study can suggest the implications as follows. As the purchase decision making process of consumer in real estate marketing, purchase and postpurchase behavior are specifically proposed. They will contribute to the theoretical progress of understanding on consumer behavior in real estate. And this study enlarges general marketing to real estate marketing by analyzing specific purchase and postpurchase behavior in real estate.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.102-113
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• 2014

This paper suggests a novel hardware architecture of a real-time rectification which is to remove vertical parallax of an image occurred in the pre-processing stage of stereo matching. As an off-line step, Matlab Toolbox which was designed by J.Y Bouguet, was used to calculate calibration parameter of the image. Then, based on the Heikkila and Silven's algorithm, rectification hardware was designed. At this point, to enhance the precision of the rectified image, floating-point unit was generated by using Xilinx Core Generator. And, we confirmed that proposed hardware design had higher precision compared to other designs while having the ability to do rectification in real-time.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.7-16
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• 2000

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It performed the division and square-toot by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.20-25
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• 2009

We propose hardware architecture of floating-point square root and inverse square root arithmetic units using lookup tables. They are used for lighting engines and shader processor for 3D graphic processing. The architecture is based on Taylor series expansion and consists of lookup tables and correction units so that the size of look-up tables are reduced. It can be applied to 32 bit floating point formats of IEEE-754 and reduced 24 bit floating point formats. The square root and inverse square root arithmetic units for 32 bit and 24 bit floating format number are designed as the proposed architecture. They can operation in a single cycle, and satisfy the precision of $10^{-5}$ required by OpenGL 1.x ES. They are designed using Verilog-HDL and the RTL codes are verified using an FPGA.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.31-38
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• 1998

This paper deals with CBS(Cycle Base Simulator) design of a 32 bit floating point DSP(Digital Signal Processor). The CBS has been developed for TMS320C30 compatible DSP and will be used to confirm the architecture, functions of sub-blocks, and control signals of the chip before the detailed logic design starts with VHDL. The outputs from CBS are used as important references at gate level design step because they give us control signals, output values of important blocks, values from internal buses and registers at each pipeline step, which are not available from the commercial simulator of DSP. In addition to core functions, it has various interfaces for efficient execution and convenient result display, CBS is verified through comparison with results from the commercial simulator for many application algorithms and its simulation speed is as fast as several tenth of that of logic simulation with VHDL. CBS in this work is for a specific DSP, but the concept may be applicable to other VLSI design.