• Title/Summary/Keyword: 보상형 스위치 구조

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Design of the New Third-Order Cascaded Sigma-Delta Modulator for Switched-Capacitor Application (스위치형 커패시터를 적용한 새로운 형태의 3차 직렬 접속형 시그마-델타 변조기의 설계)

  • Ryu Jee-Youl;Noh Seok-Ho
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2006.05a
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    • pp.906-909
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    • 2006
  • This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented in a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage.

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A Novel Third-Order Cascaded Sigma-Delta Modulator using Switched-Capacitor (스위치형 커패시터를 이용한 새로운 형태의 3차 직렬 접속형 시그마-델타 변조기)

  • Ryu, Jee-Youl;Noh, Seok-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.1
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    • pp.197-204
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    • 2010
  • This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is $1.9{\times}1.5\;mm$.

Development of Switched-Capacitor Sigma-Delta Modulator for Automotive Radars (차량 레이더용 스위치 커패시터 시그마-델타 변조기 개발)

  • Ryu, Jee-Youl;Noh, Seok-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.8
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    • pp.1887-1894
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    • 2010
  • This paper proposes a new switched-capacitor sigma-delta modulator for automotive radars. Developed modulator is used to perform high-resolution analog-to-digital conversion (ADC) of high frequency band signal in a radar system. It has supply voltage of 2.7V, and has body-effect compensated switch configuration with low voltage and low distortion. The modulator has been implemented in a $0.25{\mu}m$ double-poly and triple-metal standard CMOS process, and it has die area of $1.9{\times}1.5mm^{2}$. It showed better total harmonic distortion of 20dB than the conventional bootstrapped circuit at the supply voltage of 2.7V.

A novel PFC AC/DC converter for reducing conduction losses (도통손실 저감형 역률 보상 AC/DC 컨버터)

  • Kang, Feel-Soon;Choi, Cheul;Park, Sung-Jun;Kim, Cheul-U
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.14 no.2
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    • pp.52-58
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    • 2000
  • This paper presents a novel power factor corrected(PFC) single-stage AC/DC half-bridge converter, which features discontinuous conduction mode(DCM) and soft-switching. The reduced conduction losses are achieved by the employment of a novel powder factor correction circuitry, instead of the conventional configuration composed of a front-end rectifier followed by a boost converter. To identify the validity of the proposed converter, simulated results of 500[W] converter with 100[V] input voltage and 50[V]output voltage are presented.

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A Voltage Disturbance Detection Method for Computer Application Lods (컴퓨터 응용 부하들을 위한 전압 외란 검출 방법)

  • 이상훈;최재호
    • The Transactions of the Korean Institute of Power Electronics
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    • v.5 no.6
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    • pp.584-591
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    • 2000
  • Power Quality Compensator(PQC) has been installed to protect the sensitive loads against the voltage disturbances, such as voltage sag and interruption. In general, static switch is used for the purpose of link between utility and PQC. So transfer operation of the static switch play a important part in the PQC. Many studies on the structure and control of PQC have been progressed in active, but these researches have been rarely mentioned about any voltage-disturbances-detection method to start the PQC operation. In this paper, a new voltage-disturbances-detection algorithm for computer application loads using the CBEMA/ITIC curve is proposed for transfer operation of the static switch. The proposed detection algorithm is implemented to get fast detecting time through the comparison of instantaneous 3-phase voltage values transferred to DC values in the synchronous reference frame with the operating reference values. To get the robust characteristics against the noise, a first order digital filter is designed. The magnitude falling and phase delay caused by the filter are compensated through the error normalizing and numerical analysis using transfer function, respectively. Finally, the validity of the proposed algorithm is proved by ACSL simulation and experimental results.

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Single-Stage AC/DC Converter with Low Conduction Loss and Power Factor Correction (저 도전 손실형 단단 역률보상 교류/직류 변환기)

  • 류명효;정종진;김흥근
    • The Transactions of the Korean Institute of Power Electronics
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    • v.5 no.1
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    • pp.79-87
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    • 2000
  • 본 논문은 저 도전 손실을 갖는 새로운 단단, 단일 스위치 역률보상 부스트형 교류/직류 변환기를 소개한다. 제안한 변환기는 약간의 구조적 차이점을 제외하고 기존의 변환기와 동일하게 해석될 수 있다. 먼저, 제안한 변환기와 기존의 변환기의 동작원리를 파악하여 두 변환기의 차이점을 이해하고 1단 역률 보상 교류/직류 변환기의 구조적 문제점인 에너지 저장 커패시터에서의 직류 전압 상승을 방지하기 위한 직류 부스 전압 궤환 방식을 도입하여 제안한 변환기에 적용하였다. 100W급 변환기를 제작/실험하여 본 변환기의 타당성을 검증하였다.

Dead-time Compensation of Grid-connected Single-phase Inverter Based on SOGI (SOGI 기반 계통연계형 단상 인버터의 데드타임 보상)

  • Seong, Ui-Seok;Jeong, Byeong-Guk;Lee, Jae-Suk;Hwang, Seon-Hwan
    • Proceedings of the KIPE Conference
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    • 2016.07a
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    • pp.493-494
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    • 2016
  • 본 논문에서는 계통연계형 단상 인버터의 데드타임 영향을 보상하는 새로운 알고리즘을 제시한다. 데드타임은 전력용 반도체 스위치를 제어하기 위한 PWM 신호 출력시 인버터의 동일 레그에서 두 스위칭 소자가 동시에 턴-온 되는 경우 발생하는 단락을 방지하기 위해 삽입된다. 이러한 데드타임은 인버터 출력전압에 전원주파수의 기본파 및 홀수차 고조파를 야기하며 그로 인해 상전류 역시 왜곡이 발생된다. 본 논문에서는 H-bridge 인버터의 구조를 가지는 계통연계형 단상 인버터에서 데드타임에 의한 인버터 출력전압 및 상전류의 영향을 분석하고 계통측 상전류에 포함된 고조파 성분을 제거하기 위하여 SOGI(Second-order Generalized Integrator)를 활용한 새로운 보상 알고리즘을 제안한다. 시뮬레이션과 실험을 통해 제안하는 알고리즘의 효용성을 검증한다.

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Design of a new adaptive circuit to compensate for aging effects of nanometer digital circuits (나노미터 디지털회로의 노화효과를 보상하기위한 새로운 적응형 회로 설계)

  • Kim, Kyung Ki
    • Journal of Korea Society of Industrial Information Systems
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    • v.18 no.6
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    • pp.25-30
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    • 2013
  • In nanoscale MOSFET technology, aging effects such as Negative Bias Temperature Instability(NBTI), Hot carrier Injection(HCI), Time Dependent Dielectric Breakdown (TDDB) and so on which affect circuit reliability can lead to severe degradation of digital circuit performance. Therefore, this paper has proposed the adaptive compensation circuit to overcome the aging effects of digital circuits. The proposed circuit deploys a power gating structure with variable power switch width and variable forward body-biasing voltage in order to adaptively compensate for aging induced performance degradation, and has been designed in 45nm technology.

Sigma-Delta Modulator for Automotive Radar Systems (차량 레이더 시스템용 시그마-델타 변조기)

  • Ryu, Jee-Youl;Noh, Seok-Ho
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.05a
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    • pp.818-821
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    • 2010
  • 본 논문에서는 차량 레이더 시스템용 시그마-델타 변조기를 제안한다. 개발된 변조기는 차량 레이더 시스템에서 고주파 대역 신호의 고해상도 데이터 변환, 즉 아날로그-디지털변환을 수행하는데 사용되며 저전압 및 저 왜곡 특성을 가진 몸체효과 보상형 스위치 구조로 구현되어 있다. 제안된 변조기는 0.25 마이크론 이중 폴리 3-금속 표준 CMOS 공정으로 제작되었고, $1.9{\times}1.5mm^2$의 다이 면적을 점유한다. 제안된 회로는 2.7V의 동작 전압에서 기존의 부트스트랩형 회로보다 약 20dB 향상된 우수한 총 고조파 왜곡 특성을 보였다.

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Beam Steering Antenna Using a Dipole and a Loop (다이폴 루프 결합형 빔 조향 안테나)

  • Ha, Sang-Jun;Kim, Yong-jin; Jung, Chang-Won
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.8
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    • pp.880-885
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    • 2010
  • In this paper, we propose a reconfigurable beam steering antenna using a dipole and a loop. The radiation patterns of the two antennas were cancelled or compensated, and head for the specific direction when a dipole and a loop antenna are combined at the reasonable ratio. The structure of the antenna is very simple and planar. By changing on/ off states of switches, the proposed antenna can steer the beam direction in the x-y plane. Simulation results confirmed the steering characteristic by using two imaginary switches. The proposed antenna can change the direction of the maximum gain in the x-y plane($0^{\circ}$, ${\pm}50^{\circ}$). The proposed antenna operates in 2.5~2.56 GHz(VSWR<2). It showed that peak gain of the antenna is 1.96~2.48 dBi and overall beam width of the reconfigurable antenna covers about $125^{\circ}$.